CMOS well regions with high dopant activation level and reduced extended defects
A method of fabricating an integrated circuit (IC) is provided. The method includes the following steps: providing a substrate; forming a p-well region in the substrate; forming an n-well region in the substrate; conducting a microwave annealing at a first temperature; conducting, after the microwave annealing, a supplemental annealing at a second temperature higher than the first temperature; and fabricating a plurality of field-effect transistors (FETs) in the p-well region and the n-well region.
1 . A method of fabricating an integrated circuit (IC), the method comprising:
providing a substrate;
forming a p-well region in the substrate using a first ion implantation process;
forming an n-well region in the substrate using a second ion implantation process;
conducting, after the first ion implantation process and the second ion implantation process, a microwave annealing at a first temperature, wherein the microwave annealing is conducted at the first temperature to recover point defects created during the first and second ion implantation processes;
conducting, after the microwave annealing, a supplemental annealing at a second temperature higher than the first temperature, wherein the supplemental annealing is a non-microwave annealing, and wherein the supplemental annealing is conducted at the second temperature to activate dopants in the p-well region and the n-well region while avoiding formation of extended defects; and
fabricating a plurality of field-effect transistors (FETs) in the p-well region and the n-well region.
2 . The method of claim 1 , wherein the first temperature is below 800° C.
3 . The method of claim 1 , wherein the first temperature is below 600° C.
4 . The method of claim 1 , wherein the second temperature is above 800° C.
5 . The method of claim 1 , wherein the second temperature is above 1000° C.
6 . The method of claim 1 , further comprising:
detecting, by a temperature sensor, a temperature of the substrate; and
adjusting a microwave source based on the temperature of the substrate such that the temperature of the substrate reaches the first temperature.
7 . The method of claim 6 , wherein the temperature sensor is an infrared sensor.
8 . The method of claim 6 , further comprising:
rotating the substrate during the microwave annealing.
9 . A method of fabricating field-effect transistors (FETs), the method comprising:
providing a substrate;
forming a p-well region in the substrate using a first ion implantation process;
forming an n-well region in the substrate using a second ion implantation process;
conducting, after the first ion implantation process and the second ion implantation process, a microwave annealing at a first temperature, wherein the microwave annealing is conducted at the first temperature to recover point defects created during the first and second ion implantation processes;
conducting, after the microwave annealing, a supplemental annealing at a second temperature higher than the first temperature, wherein the supplemental annealing is a non-microwave annealing, and wherein the supplemental annealing is conducted at the second temperature to activate dopants in the p-well region and the n-well region while avoiding formation of extended defects;
forming a plurality of fin structures over the p-well region and the n-well region;
forming a plurality of source regions and a plurality of drain regions of the plurality of fin structures; and
forming a plurality of gate structures over the plurality of fin structures.
10 . The method of claim 9 , further comprising:
forming a plurality of contact structures over the plurality of source regions and the plurality of drain regions.
11 . The method of claim 9 , wherein the first temperature is below 600° C.
12 . The method of claim 9 , wherein the second temperature is above 1000° C.
13 . The method of claim 9 , wherein the supplemental annealing is one of a furnace annealing, a rapid thermal annealing (RTA), a millisecond annealing, a microsecond annealing and a laser annealing.
14 . The method of claim 9 , wherein a power of a microwave source used in the microwave annealing ranges from 50 W to 5000 W.
15 . An integrated annealing system, comprising:
a microwave annealing system configured to anneal a p-well region and an n-well region formed in a substrate on a wafer using a microwave annealing at a first temperature;
a supplemental annealing system cascaded with the microwave annealing system and configured to anneal the p-well region and the n-well region formed in the substrate using a supplemental annealing at a second temperature higher than the first temperature, wherein the supplemental annealing is a non-microwave annealing, and wherein the microwave annealing system and the supplemental annealing system are located in close proximity in a housing; and
a transfer robot located between the microwave annealing system and the supplemental annealing system and configured to transfer the wafer from the microwave annealing system to the supplemental annealing system.
16 . The integrated annealing system of claim 15 , wherein the first temperature is below 600° C.
17 . The integrated annealing system of claim 15 , wherein the second temperature is above 1000° C.
18 . The integrated annealing system of claim 15 , wherein the microwave annealing system comprises:
a chamber;
a wafer support structure configured to support the substrate;
a microwave source configured to generate a microwave radiation; and
a waveguide connecting the microwave source and the chamber and configured to guide the microwave radiation into the chamber.
19 . The integrated annealing system of claim 18 , wherein the microwave annealing system further comprises:
a temperature sensor configured to detect a temperature of the substrate; and
a control unit configured to adjust the microwave source based on the temperature of the substrate such that the temperature of the substrate reaches the first temperature.