Granted Patent B2

US 12,699,666 · App. 18/044,257 · Granted Aug 4, 2026

Inventors: Nadim Khlat (Cugnaux, FR); Christopher Truong Ngo (Queen Creek, AZ); Alexander Wayne Hietala (Phoenix, AZ)

Assignee: Qorvo US, Inc.

G06F13/362G06F13/4282H04L12/40195

Abstract

Claims (54)

1 . A hybrid bus communication circuit comprising:

a first type communication bus comprising multiple wires and configured to carry timing critical information;

a second type communication bus and a third type communication bus each consisting of a single wire and having a slower data rate than the first type communication bus, wherein the second type communication bus is configured to carry timing constrained information less time-sensitive than the timing critical information and the third type communication bus is configured to carry non-timing critical information less time-sensitive than the timing constrained information;

a master circuit coupled exclusively to the first type communication bus;

a hybrid bridge circuit coupled to the first type communication bus, the second type communication bus, and the third type communication bus; and

a plurality of multi-bus slave circuits each coupled to the master circuit via the first type communication bus and coupled to the hybrid bridge circuit via the second type communication bus;

a plurality of single-bus slave circuits coupled to the hybrid bridge circuit via the third type communication bus; and

wherein the hybrid bridge circuit and each of the plurality of multi-bus slave circuits can initiate communication over the second type communication bus via a bus contention mechanism and the hybrid bridge circuit is configured to:

receive a configuration command from the master circuit via the first type communication bus;

determine one or more configuration parameters based on the received configuration command; and

configure the determined one or more configuration parameters in at least one selected multi-bus slave circuit among the plurality of multi-bus slave circuits via the second type communication bus.

2 . The hybrid bus communication circuit of claim 1 , wherein the master circuit is configured to:

provide the configuration command to the hybrid bridge circuit via the first type communication bus to thereby cause the hybrid bridge circuit to configure the determined one or more configuration parameters in the at least one selected multi-bus slave circuit; and

provide an action command to the at least one selected multi-bus slave circuit via the second type communication bus to thereby cause the at least one selected multi-bus slave circuit to perform a defined action based on the one or more configuration parameters.

3 . The hybrid bus communication circuit of claim 2 , wherein the master circuit further provides the action command to the at least one selected multi-bus slave circuit after a predetermined delay from providing the configuration command to the hybrid bridge circuit such that the hybrid bridge circuit can configure the one or more configuration parameters in the at least one selected multi-bus slave circuit prior to the at least one selected multi-bus slave circuit receiving the action command.

4 . The hybrid bus communication circuit of claim 1 , wherein the plurality of multi-bus slave circuits each comprises a plurality of registers each comprising a plurality of bits.

5 . The hybrid bus communication circuit of claim 4 , wherein the hybrid bridge circuit is further configured to write the one or more configuration parameters into one or more of the plurality of bits in one or more of the plurality of registers comprised in the at least one selected multi-bus slave circuit.

6 . The hybrid bus communication circuit of claim 5 , wherein the master circuit is further configured to write one or more second configuration parameters directly into one or more the plurality of bits in one or more of the plurality of registers in any of the plurality of multi-bus slave circuits.

7 . The hybrid bus communication circuit of claim 6 , wherein the master circuit and the hybrid bridge circuit are configured not to write concurrently into an identical one of the plurality of bits in an identical one of the plurality of registers comprised in an identical one of the plurality of multi-bus slave circuits.

8 . The hybrid bus communication circuit of claim 1 , wherein the hybrid bridge circuit comprises a control circuit configured to:

receive the configuration command via the first type communication bus;

determine the one or more configuration parameters based on the received configuration command; and

configure the determined one or more configuration parameters in the at least one selected multi-bus slave circuit among the plurality of multi-bus slave circuits via the second type communication bus.

9 . The hybrid bus communication circuit of claim 8 , wherein the hybrid bridge circuit further comprises a memory circuit configured to store one or more lookup tables (LUTs) each predetermined to correlate a respective configuration command with one or more respective configuration parameters.

10 . The hybrid bus communication circuit of claim 9 , wherein the control circuit is further configured to:

determine a selected one of the one or more LUTs having the respective configuration command matching the received configuration command; and

determine the one or more configuration parameters as being the one or more respective configuration parameters corresponding to the selected one of the one or more LUTs.

11 . The hybrid bus communication circuit of claim 1 , wherein:

the first type communication bus is a multi-wire serial bus comprising a radio frequency front-end (RFFE) bus;

the second type communication bus is a single-wire peer-to-peer bus; and

the third type communication bus is a single-wire serial bus (SuBUS).

12 . The hybrid bus communication circuit of claim 1 , wherein the hybrid bridge circuit comprises:

a multi-wire serial bus interface circuit coupled to the first type communication bus;

a single-wire peer-to-peer bus interface circuit coupled to the second type communication bus; and

a single-wire serial bus interface circuit coupled to the third type communication bus.

13 . The hybrid bus communication circuit of claim 1 , wherein each of the hybrid bridge circuit and the plurality of multi-bus slave circuits is configured to communicate exclusively with the master circuit via the first type communication bus.

14 . The hybrid bus communication circuit of claim 1 , wherein each of the hybrid bridge circuit and the plurality of multi-bus slave circuits is configured to communicate directly with one another via the second type communication bus, independent of the master circuit.

15 . The hybrid bus communication circuit of claim 14 , wherein each of the hybrid bridge circuit and the plurality of multi-bus slave circuits is preassigned a respective access priority for accessing the second type communication bus.

16 . The hybrid bus communication circuit of claim 15 , wherein the hybrid bridge circuit is preassigned with a highest access priority.

17 . The hybrid bus communication circuit of claim 1 , wherein:

each of the plurality of single-bus slave circuits is configured to communicate exclusively with the hybrid bridge circuit via the third type communication bus; and

the hybrid bridge circuit is further configured to bridge communications between the master circuit and the plurality of single-bus slave circuits.

18 . The hybrid bus communication circuit of claim 17 , wherein the plurality of single-bus slave circuits is each configured to draw power from the master circuit via the third type communication bus.

19 . A wireless device comprising a hybrid bus communication circuit, the hybrid bus communication circuit comprises:

a first type communication bus comprising multiple wires and configured to carry timing critical information;

a second type communication bus and a third type communication bus each consisting of a single wire and having a slower data rate than the first type communication bus, wherein the second type communication bus is configured to carry timing constrained information less time-sensitive than the timing critical information and the third type communication bus is configured to carry non-timing critical information less time-sensitive than the timing constrained information;

a master circuit coupled exclusively to the first type communication bus;

a hybrid bridge circuit coupled to the first type communication bus, the second type communication bus, and the third type communication bus;

a plurality of multi-bus slave circuits each coupled to the master circuit via the first type communication bus and coupled to the hybrid bridge circuit via the second type communication bus;

a plurality of single-bus slave circuits coupled to the hybrid bridge circuit via the third type communication bus; and

wherein the hybrid bridge circuit and each of the plurality of multi-bus slave circuits can initiate communication over the second type communication bus via a bus contention mechanism and the hybrid bridge circuit is configured to:

receive a configuration command from the master circuit via the first type communication bus;

determine one or more configuration parameters based on the received configuration command; and

configure the determined one or more configuration parameters in at least one selected multi-bus slave circuit among the plurality of multi-bus slave circuits via the second type communication bus.

Assignments (1)

Continuity (2)

References Cited (269)