Granted Patent B2

US 12,705,055 · App. 17/654,449 · Granted Aug 11, 2026

Inventors: Alan Graham Alexander (Wotton-under-Edge, GB); Simon Christian Knowles (Corston, GB); Mrudula Chidambar Gore (Bath, GB); Jonathan Ferguson (Bristol, GB)

Assignee: GRAPHCORE LIMITED

G06F9/30065G06F9/30076G06F9/3808G06F9/381G06F12/0875

Abstract

Claims (23)

1 . A method of operating a processor having a barrel-threaded execution unit configured to run a plurality of concurrent threads each in a different respective one of a repeating sequence of interleaved time slots, the method comprising:

running a program comprising the plurality of concurrent threads on the processor through the execution unit, a first thread of the threads including a first instance of a repeat instruction, the repeat instruction being a machine code instruction that is defined by an opcode and that takes a repeat count operand;

executing the first instance of the repeat instruction, including, in response to the opcode of the repeat instruction:

determining that a repeat cache of the processor is not claimed;

caching a first portion of code from the first thread into the repeat cache;

recording the repeat cache as claimed; and

executing the first portion of code a first number of times according to the repeat count operand of the first instance of the repeat instruction, taking at least one successive repetition of the first portion of code from the repeat cache; and

resetting a state of the repeat cache as unclaimed once at least the first thread has finished executing the first portion of code the first number of times;

the method further including:

in the first thread, executing a second instance of the repeat instruction in which the repeat count operand is zero, the second instance of the repeat instruction causing the execution unit to cache a second portion of code from the first thread into the repeat cache and skip execution of the second portion of code in the first thread; and

executing a third instance of the repeat instruction included in a second thread of said threads, including, in response to the opcode of the repeat instruction, executing the second portion of code from the repeat cache a second number of times according to the repeat count operand of the third instance of the repeat instruction, taking at least one successive repetition of the second portion of code from the repeat cache.

2 . The method of claim 1 , wherein said first portion of code is a portion following the first instance of the repeat instruction in the first thread.

3 . A processor comprising:

an execution unit configured to execute instances of instructions defined in an instruction set, wherein the execution unit is a barrel-threaded execution unit configured to run a plurality of concurrent threads each in a different respective one of a repeating sequence of interleaved time slots; and

a repeat cache having an associated state recording whether or not the repeat cache is currently claimed by one of the threads;

wherein the instructions defined in the instruction set include a repeat instruction which takes a repeat count operand, the execution unit being configured so as:

in response to the opcode of the repeat instruction and in response to the repeat cache being not currently claimed according to said state and a first instance of the repeat instruction being executed in a first thread of said threads:

to cache a first portion of code from the first thread into the repeat cache, to modify said state to record the repeat cache as claimed, and to execute said first portion of code a respective number of times, taking each successive repetition of the first portion of code from the repeat cache;

wherein the processor is configured to reset said state to record the repeat cache as unclaimed again once at least the first thread has finished executing the first portion of code the respective number of times;

the execution unit further configured to, after the reset of said state:

in the first thread, execute a second instance of the repeat instruction in which the repeat count operand is zero, the second instance of the repeat instruction causing the execution unit to cache a second portion of code from the first thread into the repeat cache and skip execution of the second portion of code in the first thread; and

execute a third instance of the repeat instruction included in a second thread of said threads, including, in response to the opcode of the repeat instruction, executing the second portion of code from the repeat cache a second number of times according to the repeat count operand of the third instance of the repeat instruction, taking at least one successive repetition of the second portion of code from the repeat cache.

4 . The processor of claim 3 , wherein said first portion of code is a portion following the first instance of the repeat instruction in the first thread.

Assignments (1)

Priority Claims (1)

Continuity (2)

References Cited (37)