Singulation of integrated circuit package substrates with glass cores
An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core includes a first surface, a second surface opposite the first surface, a sidewall between the first surface and the second surface, and a corner region where the first sidewall meets the first surface. A first build-up layer is on at least the first surface. In some embodiments, the corner region comprises a recess and a dielectric material within the recess. In other embodiments, the corner region comprises a first compressive stress and the glass core comprises a second region. The second region comprises a second compressive stress. The first compressive stress is greater than the second compressive stress.
1 . An integrated circuit (IC) device comprising:
a substrate comprising a glass core, the glass core comprising:
a first surface;
a second surface opposite the first surface;
a first sidewall between the first surface and the second surface;
a corner region where the first sidewall meets the first surface, wherein the corner region comprises a portion of the first sidewall; and
a second region on the first sidewall, wherein the second region is spaced away from the first and second surfaces;
a first build-up layer on at least the first surface;
wherein the corner region comprises a first compressive stress, the second region comprises a second compressive stress, and the first compressive stress is greater than the second compressive stress.
2 . The IC device of claim 1 , wherein the corner region comprises a recess and a dielectric material within the recess.
3 . The IC device of claim 2 , wherein the recess comprises a third surface that is other than perpendicular to either the first surface or the first sidewall.
4 . The IC device of claim 3 , wherein the third surface is planar or curved.
5 . The IC device of claim 1 , wherein the corner region comprises a recess open to the first sidewall and a dielectric material within the recess, and the recess comprises a third sidewall approximately parallel with the first sidewall, and a fourth sidewall approximately parallel with the first surface.
6 . The IC device of claim 1 ,
wherein the corner region comprises a first porosity percentage, the second region comprises a second porosity percentage, and the first porosity percentage is greater than the second porosity percentage.
7 . The IC device of claim 1 , wherein the corner region comprises a first refractive index, the second region comprises a second refractive index, and the first refractive index is different from the second refractive index.
8 . The IC device of claim 1 , wherein the corner region comprises a first photoelasticity parameter value, the second region comprises a second photoelasticity parameter value, and the first photoelasticity parameter value is different from the second photoelasticity parameter value.
9 . The IC device of claim 1 , wherein the first sidewall further comprises an artifact of a mechanical sawing process.
10 . The IC device of claim 1 , wherein the first build-up layer comprises a metallization layer and a dielectric material layer.
11 . The IC device of claim 1 , wherein the corner region spans a distance from the first sidewall in a direction parallel to the first surface, and the distance is between about 25 and 75 microns.
12 . The IC device of claim 1 , wherein the glass core comprises a thickness of between 200 and 1600 microns, the corner region spans a distance from the first surface in a direction parallel to the first sidewall, and the distance is between about 15 and 25 percent of the thickness of the glass core.
13 . The IC device of claim 1 , further comprising a second build-up layer on the second surface, the second build-up layer comprising a metallization layer and a dielectric material layer.
14 . An integrated circuit (IC) device comprising:
a substrate comprising glass core, the glass core comprising:
a first surface;
a second surface opposite the first surface;
a first sidewall between the first surface and the second surface;
a corner region where the first sidewall meets the first surface; and
a second region;
a first build-up layer on at least the first surface; and
an IC die coupled with the first build-up layer;
wherein the corner region comprises a first porosity percentage, the second region comprises a second porosity percentage, and the first porosity percentage is greater than the second porosity percentage.
15 . The IC device of claim 14 , wherein the corner region comprises recess having a third surface that is other than perpendicular to either the first surface or the first sidewall.
16 . The IC device of claim 14 ,
wherein the corner region comprises a first compressive stress, the second region comprises a second compressive stress, and the first compressive stress is greater than the second compressive stress.