Voltage regulation device with dual-loop design
A voltage regulation device includes: a first low-dropout (LDO) regulator, a second LDO regulator and a signal coupling circuit. The first LDO regulator is configured to receive an input voltage of the voltage regulation device and accordingly generate and stabilize an output voltage of the voltage regulation device. The second LDO regulator is coupled in parallel with the first LDO regulator, and configured to provide supplementary regulation to further stabilize the output voltage. The signal coupling circuit is coupled between the first LDO regulator and the second LDO regulator, configured to apply a voltage provided by second LDO regulator to the first LDO regulator, thereby modulating an operation of the first LDO regulator.
1 . A voltage regulation device, comprising:
a first low-dropout (LDO) regulator, configured to receive an input voltage of the voltage regulation device and accordingly generate and stabilize an output voltage of the voltage regulation device, comprising:
a first differential amplifier, configured to generate a first driving voltage based on a difference between the output voltage and a reference voltage;
a second LDO regulator, coupled in parallel with the first LDO regulator, configured to provide supplementary regulation to further stabilize the output voltage, comprising:
a second differential amplifier, configured to generate a second driving voltage based on the difference between the output voltage and the reference voltage, wherein a size of the second differential amplifier is smaller than that of the first differential amplifier, and geometric parameters of one or more transistors included in the second differential amplifier are smaller than those of one or more corresponding transistors included in the first differential amplifier; and
a signal coupling circuit, coupled between the first LDO regulator and the second LDO regulator, configured to apply a voltage provided by second LDO regulator to the first LDO regulator, thereby modulating an operation of the first LDO regulator.
2 . The voltage regulation device of claim 1 , wherein the first LDO regulator further comprises:
a first pass transistor, coupled to the first differential amplifier, driven by the first driving voltage to regulate the output voltage; and
wherein the second LDO regulator further comprises:
a second pass transistor, coupled to the second differential amplifier, driven by the second driving voltage to regulate the output voltage.
3 . The voltage regulation device of claim 2 , wherein the first differential amplifier has a first input terminal, a second input terminal and an output terminal; the first pass transistor has a control terminal, a first terminal and a second terminal; the first input terminal of the first differential amplifier is coupled to the reference voltage, the second input terminal of the first differential amplifier is coupled to the second terminal of first pass transistor and the output voltage, the output terminal of the first differential amplifier is coupled to the control terminal of the first pass transistor, and the first terminal of the first pass transistor is coupled to the input voltage.
4 . The voltage regulation device of claim 2 , wherein the second differential amplifier has a first input terminal, a second input terminal and an output terminal; the second pass transistor has a control terminal, a first terminal and a second terminal; the first input terminal of the second differential amplifier is coupled to the reference voltage, the second input terminal of the second differential amplifier is coupled to the second terminal of second pass transistor and the output voltage, the output terminal of the second differential amplifier is coupled to the control terminal of the second pass transistor, and the first terminal of the second pass transistor is coupled to the input voltage.
5 . A voltage regulation device, comprising:
a first low-dropout (LDO) regulator, configured to receive an input voltage of the voltage regulation device and accordingly generate and stabilize an output voltage of the voltage regulation device, comprising:
a first differential amplifier, configured to generate a first driving voltage based on a difference between the output voltage and a reference voltage; and
a first pass transistor, coupled to the first differential amplifier, driven by the first driving voltage to regulate the output voltage;
a second LDO regulator, coupled in parallel with the first LDO regulator, configured to provide supplementary regulation to further stabilize the output voltage, comprising:
a second differential amplifier, configured to generate a second driving voltage based on the difference between the output voltage and the reference voltage; and
a second pass transistor, coupled to the second differential amplifier, driven by the second driving voltage to regulate the output voltage; and
a signal coupling circuit, coupled between the first LDO regulator and the second LDO regulator, configured to apply a voltage provided by second LDO regulator to the first LDO regulator, thereby modulating an operation of the first LDO regulator, comprising:
a current mirror circuit, coupled to the input voltage and an output terminal of the second differential amplifier, configured to generate an output current according to an input current that is generated based on the second driving voltage provided by the second differential amplifier; and;
a coupling capacitor, coupled between an output terminal of the current mirror circuit and an output terminal of the first differential amplifier, configured to facilitate coupling of voltage fluctuation that is induced by the output current of the current mirror circuit to the output terminal of the first differential amplifier.
6 . The voltage regulation device of claim 5 , wherein the current mirror circuit comprises:
a first transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of first transistor is coupled to the first terminal of the first transistor;
a second transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of second transistor is coupled to the control terminal of the first transistor, and the first terminal of the second transistor is coupled to the output terminal of the current mirror circuit; and
a third transistor, having a control terminal, a first terminal and a second terminal, wherein the control terminal of third transistor is coupled to the output terminal of the second differential amplifier and the second terminal of the third transistor is coupled to the first terminal of the first transistor.
7 . The voltage regulation device of claim 6 , wherein the current mirror circuit comprises:
an enablement circuit coupled to the first, second and third transistors, configured to selectively activate or deactivate the current mirror circuit according to at least one enablement signal.
8 . The voltage regulation device of claim 7 , wherein the enablement circuit comprises:
a first switching transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the first switching transistor is coupled to a first enablement signal, the first terminal of the first switching transistor is coupled to the input voltage and the second terminal of the first switching transistor is coupled to the first terminal of the third transistor;
a second switching transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the second switching transistor is coupled to a second enablement signal and the second terminal of the second switching transistor is coupled to the output terminal of the current mirror circuit, wherein the second enablement signal is an inverted version of the first enablement signal; and
a third switching transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the third switching transistor is coupled to the first enablement signal, the first terminal of the third switching transistor is coupled to the input voltage and the second terminal of the third switching transistor is coupled to the first terminal of the second switching transistor.