Method for operating memory device
Provided is a method for operating a memory device including performing a first setting operation on a first operation, reading map data based on the first setting operation, and performing a second setting operation on a second operation.
1 . A memory device comprising:
a memory cell array in which a first setting data on a first operation, a second setting data on a second operation, and map data are stored, the first operation including an SLC read; and
a control logic comprising a dump down circuit configured to verify validity of a setting data and a latch in which the setting data having passed through the verification of validity is stored,
wherein the first setting data is stored in the latch to perform a first setting operation, and
wherein the map data are read after the first setting operation.
2 . The memory device of claim 1 , wherein the second operation includes a memory operation excluding the SLC read.
3 . The memory device of claim 2 , wherein the memory operation excluding the SLC read includes a SLC program, a SLC erase, and multi-bit-based read, program, and erase.
4 . The memory device of claim 1 , wherein the performing of the first setting operation includes reading a defensive code, and
wherein the memory device is further configured to read data by using the defensive code based on an uncorrectable error correction code (UECC) being generated at a time of a read operation.
5 . The memory device of claim 1 , wherein the first operation includes a SLC read operation on a chip to which a main firmware code is programmed, and
wherein the memory device, before the reading of the map data, is further configured to:
execute a boot loader by SLC-reading a boot-loader code programmed to a memory cell array; and
allow the boot loader to execute the main firmware code.
6 . The memory device of claim 5 , wherein the executing the boot loader includes:
reading ROM code programmed to a ROM of the memory device to SLC-read the boot-loader code programmed to the memory cell array.
7 . The memory device of claim 5 , wherein the memory device, after the executing the main firmware code, is further configured to perform a third setting operation on a SLC program and a SLC erase, and
wherein the second operation includes a multi-bit-based read, program, and erase.
8 . The memory device of claim 1 , wherein the memory device, before the performing the first setting operation on the first operation, is further configured to turn on the memory device after a sudden power off (SPO) occurs in the memory device, and
wherein the first operation includes SLC read, SLC program, and SLC erase.
9 . The memory device of claim 8 , wherein the second operation includes multi-bit-based read, program, and erase.
10 . The memory device of claim 1 , wherein the verifying of validity of the setting data includes:
duplicating and expanding respective bits of the setting data into n bits and programming the n bits of setting data to the memory cell array; and
passing through verification of validity based on the setting data matching bits of equal to or greater than a reference number from among the n bits, where n is an integer that is greater than 1.
11 . The memory device of claim 10 , wherein the reference number is 0.75*n.
12 . The memory device of claim 1 , wherein the first operation includes a non-plane independent read (non-PIR) operation, and
wherein the second operation includes a PIR operation.
13 . The memory device of claim 1 , wherein the latch includes an electrical-fuse (e-fuse).
14 . A memory system comprising:
a memory device comprising a memory cell array in which a first setting data on a first operation, a second setting data on a second operation, and map data are stored and a control logic configured to verify validity of a setting data and store the setting data having passed through the verification of validity in a latch, the first operation including an SLC read; and
a memory processor configured to output a first command for the first setting data, a second command for the map data, and a third command for the second setting data,
wherein the memory device is configured to store the first setting data in the latch to perform a first setting operation and output a signal for a ready state of the memory device in response to completion of the first setting operation
wherein the memory processor is configured to output the second command in response to outputting the signal for the ready state of the memory device.
15 . The memory system of claim 14 , wherein the second operation includes a memory operation excluding the SLC read.
16 . The memory system of claim 15 , wherein the memory operation excluding the SLC read includes a SLC program, a SLC erase, and multi-bit-based read, program, and erase.
17 . The memory system of claim 15 , wherein the second setting data is stored in the latch to perform a second setting operation in background of the memory device.
18 . The memory system of claim 14 , wherein the memory device is configured to read map data in response to the second command, and
wherein the memory system is configured to process a request by using the map data.
19 . A memory system comprising:
a memory device comprising a first region in which a first setting data on a first operation and map data are stored and a second region in which a second setting data on a second operation are stored; and is configured to verify validity of a setting data and store the setting data having passed through the verification of validity in a latch, the first operation including an SLC read; and
a memory processor configured to perform a first setting operation on a first operation on the first region, read the map data after the first setting operation, and perform a second setting operation on the second region,
wherein the first setting data is stored in the latch to perform the first setting operation.
20 . The memory system of claim 19 , wherein the first region is a die or a plane of the memory device.