Memory system capable of converting data
A memory system is connectable to a host. A memory system includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of blocks, each of which is a unit of an erase operation. The controller is electrically connected to the non-volatile memory and controls the non-volatile memory. The controller receives first data from the host. The controller generates third data from the first data by randomizing the first data using second data that has a different value each time the data erase operation is executed on a first block among the plurality of blocks. The controller writes the second data to the non-volatile memory and the third data to the first block.
1 . A memory system connectable to a host, comprising:
a first non-volatile memory including a plurality of blocks, each of the plurality of blocks being a unit for a data erase operation;
a controller electrically connected to the first non-volatile memory and configured to:
receive first data from the host;
randomize the first data using a first randomization key to generate third data;
randomize fourth data using the first randomization key to generate fifth data;
write the first randomization key to the first non-volatile memory;
write the third data and the fifth data to a first block among the plurality of blocks; and
in response to receiving, from the host, a request for updating data stored in the first block,
receive sixth data from the host;
randomize the sixth data using a second randomization key to generate eighth data, the second randomization key being different from the first randomization key;
derandomize the fifth data using the first randomization key to obtain the fourth data;
randomize the obtained fourth data using the second randomization key to generate ninth data;
write the second randomization key to the first non-volatile memory; and
write the eighth data and the ninth data to the first block.
2 . The memory system according to claim 1 , wherein
the first randomization key is based on a count of the data erase operation executed on the first block.
3 . The memory system according to claim 2 , wherein
the first randomization key is also based on a count of the data erase operation executed on a second block among the plurality of blocks.
4 . The memory system according to claim 1 , wherein
the first randomization key is based on a timing of the data erase operation executed on the first block.
5 . The memory system according to claim 1 , wherein
the first randomization key is based on information about the first data.
6 . The memory system according to claim 5 , wherein
the information is at least part of identification information of the first data.
7 . The memory system according to claim 5 , wherein
the information is at least part of version information of the first data.
8 . The memory system according to claim 1 , wherein
the first randomization key is based on a count or timing of a write operation of the first data to the first block.
9 . The memory system according to claim 1 , wherein
the first data is first firmware, and the request is a request for firmware update, and
the first randomization key is included in information used for an update process or a restoration process of the first firmware.
10 . The memory system according to claim 1 , wherein
the controller is further configured to write the second data-first randomization key to the first block.
11 . The memory system according to claim 10 , wherein
the controller is further configured to:
write the third data to a first area in the first block; and
write the first randomization key to a second area in the first block, the second area being different from the first area.
12 . The memory system according to claim 11 , wherein
the controller is further configured to:
write the second randomization key to the second area;
write the eighth data to the first area; and
write the ninth data to a third area in the first block, the third area being different from the first area.
13 . The memory system according to claim 1 , wherein
the controller is further configured to:
read the written first randomization key and the third data from the first non-volatile memory; and
derandomize the third data using the first randomization key to obtain the first data.
14 . The memory system according to claim 1 , wherein
the controller is further configured to, in response to receiving the request, read the written first randomization key and the fifth data from the first block.
15 . The memory system according to claim 1 , further comprising:
a second non-volatile memory where a first key is stored, wherein
the controller is electrically connected to the second non-volatile memory and further configured to:
randomize the first randomization key using the first key to generate tenth data; and
write the tenth data to the first non-volatile memory.
16 . The memory system according to claim 15 , wherein
the controller is further configured to:
read the first key from the second non-volatile memory;
read the third data from the first block;
read the tenth data from the first non-volatile memory;
derandomize the tenth data using the first key to obtain the first randomization key; and
derandomize the third data using the first randomization key to obtain the first data.
17 . The memory system according to claim 1 , wherein
each of the plurality of blocks includes a memory cell;
the plurality of blocks further includes a third block different from the first block;
the controller is further configured to:
write data of a first number of bits to the memory cell in the first block; and
write data of a second number of bits to the memory cell in the third block, the second number being larger than the first number.
18 . The memory system according to claim 1 , wherein
the controller is further configured to:
in response to receiving a command for writing the first data from the host,
execute the data erase operation to the first block; and
after the data erase operation, write the third data to the first block.
19 . The memory system according to claim 1 , wherein
the controller is configured to randomize data using a variable randomization key that has a different value each time the data erase operation is executed on the first block, the variable randomization key including the first randomization key used to randomize the first data and the fourth data, and the second randomization key used to randomize the sixth data.
20 . A memory system connectable to a host, comprising:
a first non-volatile memory including a plurality of blocks, each of the plurality of blocks being a unit for a data erase operation, and the plurality of blocks including a first block;
a controller electrically connected to the first non-volatile memory and configured to:
receive first data from the host;
randomize the first data using a first randomization key to generate third data;
write the first randomization key to the first non-volatile memory;
write the third data to the first block; and
in response to receiving, from the host, a request for updating data stored in the first block,
derandomize the third data using the first randomization key to obtain the first data;
randomize the first data using a second randomization key to generate fifth data, the second randomization key being different from the first randomization key;
write the fifth data to the first block; and
write the second randomization key to the first non-volatile memory.