Masking sparse inputs and outputs in neural network array
Numerous examples are disclosed of a masking circuit for inputs and outputs in a neural network array. In one example, a system comprises a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and row circuits for respective rows in the neural network array, the row circuits comprising a masking circuit to prevent an application of a sparse input to one or more rows in the array when a condition is satisfied.
1 . A system comprising:
a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and
row circuits for respective rows in the neural network array, each row circuit comprising:
a row input detector to assert a disabling signal if (i) row input data for the row is equal to ‘0’; or (ii) the row input data for the row is less than or equal to a low threshold non-zero value; or (iii) the row input data for the row is greater than or equal to a high threshold value; and
disabling logic to disable the row in response to the disabling signal.
2 . The system of claim 1 , wherein the row circuit for each row comprises logic and a buffer.
3 . The system of claim 2 , wherein the system comprises AND logic receiving all outputs from the buffers to generate a neural read disable signal to prevent application of inputs signals to the rows in the neural network array.
4 . The system of claim 3 , wherein the system comprises OR logic and an inverter for each row.
5 . The system of claim 4 , wherein the system comprises AND logic to generate an output in response to an output of respective inverters of the rows.
6 . The system of claim 1 , wherein each row circuit comprises OR logic receiving row input data for the row.
7 . A system comprising:
a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and
row circuits for respective rows in the neural network array, the row circuits comprising a masking circuit to prevent application of a sparse input to one or more rows in the array when a condition is satisfied, wherein the condition is row input data for all rows is equal to ‘0’; and
wherein the masking circuit comprises OR logic receiving row input data for the row, wherein the OR logic for a first row receives a “0” on an input and the OR logic for all other rows receives an output from the OR logic for a preceding row.
8 . The system of claim 1 , wherein each row circuit comprises OR logic receiving row input data for the row and an NMOS transistor coupled to a load.
9 . The system of claim 1 , wherein each row circuit comprises an inverter receiving a single bit in the row input data for the row.
10 . The system of claim 9 , wherein system comprises AND logic to generate an output in response to the output of respective inverters.
11 . A system comprising:
a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and
row circuits for respective rows in the neural network array, the row circuits comprising a masking circuit to prevent application of a sparse input to one or more rows in the array when a condition is satisfied, wherein the condition is row input data for all rows is equal to ‘0’; and
wherein the masking circuit comprises an NMOS transistor comprising a gate receiving a single bit in the row input data for the row and a drain coupled to a load.
12 . A system comprising:
a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and
row circuits for respective rows in the neural network array, the row circuits comprising a masking circuit to prevent application of a sparse input to one or more rows in the array when a condition is satisfied;
wherein the masking circuit prevents an application of an input signal to one or more rows in the array by preventing one or more of a digital-to-analog converter and an analog-to-digital converter from being activated when the condition is satisfied, wherein the condition comprises for a respective row in the array (i) row input data for the row is equal to ‘0’; or (ii) the row input data for the row is less than or equal to a low threshold non-zero value; or (iii) the row input data for the row is greater than or equal to a high threshold value.
13 . A method comprising:
receiving row input data for respective rows in a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and
preventing an application of an input signal derived from an associated row input data by one or more of a digital-to-analog converter and an analog-to-digital converter for a row in the array for which (i) row input data for the row is equal to ‘0’; or (ii) the row input data for the row is less than or equal to a low threshold non-zero value; or (iii) the row input data for the row is greater than or equal to a high threshold value.
14 . A method comprising:
receiving row input data for respective rows in a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and
preventing an application of an input signal derived from an associated row input data for a row in the array for which the row input data is equal to or below a low threshold or above a high threshold value;
wherein the preventing comprises preventing one or more of a digital-to-analog converter and an analog-to-digital converter from being activated when the row input data for respective rows is less than or equal to a low threshold or greater than or equal to a high threshold value.