Granted Patent B2

US 12,724,588 · App. 17/743,506 · Granted Sep 1, 2026

Inventor: Thomas Eric Guttenberger (Keego Harbor, MI)

G06F7/5443

Abstract

Claims (74)

1 . A computer processor for executing Multiply Accumulate operations comprising:

a multiplication lookup table (“LUT”) stored in memory for a multiplication of two numbers; and

an addition LUT stored in memory for an addition of the two numbers;

wherein the multiplication LUT registers assignments correspond to the two numbers of a multiplication operation;

wherein the multiplication LUT returns a number resulting from the multiplication operation with minimum absolute error as represented in low precision binary code;

wherein the multiplication LUT returns a number with a magnitude in a range from 0 to 1;

wherein the multiplication LUT returns a number associated with register addresses for addition LUTs;

wherein the addition LUT registers assignments correspond to the two numbers of the operation;

wherein the addition LUT is limited to operating on numbers of a same sign;

wherein the addition LUT is limited to operating on numbers of a same base 2 exponent;

wherein the addition LUT returns a number encoded in a range between 0 and an input exponent minus one;

wherein the addition LUT returns numbers rounded higher or lower in equal proportion for each encoding magnitude where an exact return encoding is not available;

wherein the addition LUT returns a number in the same encoding format as the two numbers used to determine register address;

wherein a count of clock cycles is used to calculate a base-2 exponent of a sum of a plurality of terms, each of the plurality of terms being in a range of zero (0) to one (1);

wherein, the base-2 exponent of the sum corresponds to an upper bound of a range of the sum expressed in powers of two (2);

wherein, the sum is calculated using the addition LUT;

wherein the count of clock cycles corresponds to a time spent in calculating the sum of the plurality of terms;

wherein the count of clock cycles is calculated from a count of the plurality of terms being added, a second count of clock cycles spent for each addition between the plurality of terms, and a static buffer;

wherein, the static buffer corresponds to a third count of additional clock cycles spent when a base-2 exponent of the sum increases.

2 . The processor of claim 1 , wherein the two numbers are in the range from −1 to 1.

3 . The processor of claim 1 , wherein input numbers are rounded to 7 bit, 8 bit, 9 bit, or 10 bit encodings.

4 . The processor of claim 1 , wherein the results of the multiplication operation are bifurcated according to sign to opposite ends of a number cache.

5 . The processor of claim 1 , wherein an addition operation between a final positive and negative sums is done via binary arithmetic.

6 . A computer system comprising a plurality of computer processors of claim 1 .

7 . The computer system of claim 6 , wherein input data are distributed among the processors and multiply accumulate functions are executed in parallel.

8 . The computer system of claim 6 , wherein the plurality of computer processors are caused to distribute a computational load among the processors and execute multiply accumulate functions in parallel.

9 . The computer system of claim 6 , wherein various encoding schemes for each individual processor are used.

10 . The computer system of claim 6 , wherein different numbers of bits for different levels of precision of encodings for each individual processor are used.

11 . A method comprising:

a multiplication lookup table (“LUT”) stored in memory for a multiplication of two numbers; and

an addition LUT stored in memory for an addition of the two numbers;

wherein the multiplication LUT register assignments correspond to the two input numbers of a multiplication operation;

wherein the multiplication LUT returns a number resulting from the multiplication operation with minimum absolute error as represented in low precision binary code;

wherein the multiplication LUT returns a number of with a magnitude in a range from 0 to 1;

wherein the multiplication LUT returns a number associated with register addresses for addition LUTs;

wherein the addition LUT register assignments correspond to the two input numbers of the operation;

wherein the addition LUT is limited to operating on numbers of a same sign;

wherein the addition LUT is limited to operating on numbers of a same base 2 exponent;

wherein the addition LUT returns a number encoded in a range between 0 and an input exponent minus one;

wherein the addition LUT returns numbers rounded higher or lower in equal proportion for each encoding magnitude where an exact return encoding is not available;

wherein the addition LUT returns a number in the same encoding format as the two numbers used to determine register address;

wherein a count of clock cycles is used to calculate a base-2 exponent of a sum of a plurality of terms, each of the plurality of terms being in a range of zero (0) to one (1);

wherein, the base-2 exponent of the sum corresponds to an upper bound of a range of the sum expressed in powers of two (2);

wherein, the sum is calculated using the addition LUT;

wherein the count of clock cycles corresponds to a time spent in calculating the sum of the plurality of terms;

wherein the count of clock cycles is calculated from a count of the plurality of terms being added, a second count of clock cycles spent for each addition between the plurality of terms, and a static buffer;

wherein, the static buffer corresponds to a third count of additional clock cycles spent when a base-2 exponent of the sum increases.

12 . The method of claim 11 , wherein the two numbers are in the range from −1 to 1.

13 . The method of claim 11 , wherein input numbers are rounded to 7 bit, 8 bit, 9 bit, or 10 bit encodings.

14 . The method of claim 11 , wherein the results of the multiplication operation are bifurcated according to sign to opposite ends of a number cache.

15 . The method of claim 11 , wherein an addition operation between a final positive and negative sums is done via binary arithmetic.

16 . A non-transitory machine-readable medium comprising:

a multiplication lookup table (“LUT”) stored in memory for a multiplication of two numbers; and

an addition LUT stored in memory for an addition of the two numbers;

wherein the multiplication LUT register assignments correspond to the two numbers of a multiplication operation;

wherein the multiplication LUT returns a number resulting from the multiplication operation with minimum absolute error as represented in low precision binary code;

wherein the multiplication LUT returns a number of magnitude in a range from 0 to 1;

wherein the multiplication LUT returns a number associated with register addresses for addition LUTs;

wherein the addition LUT register assignments correspond to the two input numbers of the operation;

wherein the addition LUT is limited to operating on numbers of a same sign;

wherein the addition LUT is limited to operating on numbers of a same base 2 exponent;

wherein the addition LUT returns a number encoded in a range between 0 and an input exponent minus one;

wherein the addition LUT returns numbers rounded higher or lower in equal proportion for each encoding magnitude where an exact return encoding is not available;

wherein the addition LUT returns a number in the same encoding format as the two numbers used to determine register address;

wherein a count of clock cycles is used to calculate a base-2 exponent of a sum of a plurality of terms, each of the plurality of terms being in a range of zero (0) to one (1);

wherein, the base-2 exponent of the sum corresponds to an upper bound of a range of the sum expressed in powers of two (2);

wherein, the sum is calculated using the addition LUT;

wherein the count of clock cycles corresponds to a time spent in calculating the sum of the plurality of terms;

wherein the count of clock cycles is calculated from a count of the plurality of terms being added, a second count of clock cycles spent for each addition between the plurality of terms, and a static buffer;

wherein, the static buffer corresponds to a third count of additional clock cycles spent when a base-2 exponent of the sum increases.

17 . The non-transitory machine-readable medium of claim 16 , wherein the two numbers are in the range from −1 to 1.

18 . The non-transitory machine-readable medium of claim 16 , wherein input numbers are rounded to 7 bit, 8 bit, 9 bit, or 10 bit.

19 . The non-transitory machine-readable medium of claim 16 , wherein the results of the multiplication operation are bifurcated according to sign to opposite ends of a number cache.

20 . The non-transitory machine-readable medium of claim 16 , wherein the addition operation between a final positive and negative sums is done via binary arithmetic.

Continuity (1)

References Cited (34)