Systems and methods for parallel data processing
Systems and methods for parallel data processing. In some embodiments, the system includes: a first processing chain; and a second processing chain, the first processing chain including: a first core; a second core; and a first inter-core bus connecting the second core of the first processing chain to the first core of the first processing chain the system being configured to forward an output of a calculation of the first processing chain to the second processing chain.
1 . A system, comprising:
a first processing chain; and
a second processing chain,
the first processing chain comprising:
a first core;
a second core; and
a first inter-core bus connecting the second core of the first processing chain to the first core of the first processing chain; and
the system being configured to forward an output of a calculation of the first processing chain to the second processing chain, wherein the first core verifies a speculative operation done by the second core.
2 . The system of claim 1 , wherein the first core of the first processing chain comprises:
a memory; and
a packet processing circuit,
the packet processing circuit being configured:
to receive a packet comprising instructions; and
to store the instructions in the memory.
3 . The system of claim 1 , wherein the first processing chain is configured:
to perform, in the first core of the first processing chain, a first calculation based on a first speculative value;
to perform, in the second core of the first processing chain, a second calculation based on a second speculative value; and
to validate the first speculative value,
wherein the forwarding of the output of the first calculation to the second processing chain is based on the validating.
4 . The system of claim 1 , wherein the system is configured to perform a number of speculative operations using a number of cores based on the number of speculative operations.
5 . The system of claim 1 , further comprising a first inter-chain bus,
wherein an initial core of the first processing chain is connected, through the first inter-chain bus, to an initial core of the second processing chain.
6 . The system of claim 5 , further comprising:
a third processing chain; and
a second inter-chain bus,
wherein an initial core of the first processing chain is connected, through the second inter-chain bus, to an initial core of the third processing chain.
7 . The system of claim 1 , further comprising a packet scheduler connected to the first processing chain and to the second processing chain, the packet scheduler being configured to send, to each of the first processing chain and the second processing chain, packets comprising instructions, parameters, and input data.
8 . The system of claim 1 , further comprising a packet scheduler connected to the first processing chain, the packet scheduler being configured:
to send a first sequence of symbols to the first core of the first processing chain, for testing for a second sequence of symbols; and
to send a third sequence of symbols to a first core of the second processing chain, for testing for the second sequence of symbols,
wherein the first sequence of symbols overlaps with the third sequence of symbols.
9 . The system of claim 8 , wherein the first sequence of symbols overlaps with the third sequence of symbols in an overlapped area having a size greater than the second sequence of symbols.