Data organization for logical to physical table compression
Methods, systems, and devices for data organization for logical to physical table compression are described. The memory system may identify a region that includes one or more logical addresses associated with discontinuous corresponding physical addresses. The memory system may include a plurality of regions of logical addresses and a plurality of memory cells arranged according to a plurality of physical addresses. The memory system may determine a period of inactivity of access operations on the plurality of memory cells and rearrange, during the period of inactivity, information stored within the discontinuous corresponding physical addresses to be within continuous physical addresses of the plurality of physical addresses.
1 . A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
identify, within the memory system, a region having one or more logical addresses associated with discontinuous corresponding physical addresses in response to a quantity of the one or more logical addresses associated with the discontinuous corresponding physical addresses satisfying a threshold; and
rearrange, during a period of inactivity of access operations associated with the memory system, information stored within the discontinuous corresponding physical addresses to be within continuous physical addresses of the memory system.
2 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
record a value of each factor of a plurality of factors associated with the region of the memory system, the plurality of factors including the quantity of the one or more logical addresses, wherein the region is identified in response to the value of one or more factors of the plurality of factors satisfying one or more corresponding thresholds.
3 . The memory system of claim 2 , wherein the plurality of factors further comprise a write amplify factor associated with the region, a read count for the region, or both.
4 . The memory system of claim 3 , wherein the processing circuitry is further configured to cause the memory system to:
set a first threshold for a first factor of the plurality of factors in accordance with the value of the write amplify factor.
5 . The memory system of claim 2 , wherein the value of a first factor of the plurality of factors satisfies a first threshold and the value of a second factor of the plurality of factors fails to satisfy a second threshold, wherein the region is identified in response to the value of the first factor satisfying the first threshold in accordance with a second priority of the second factor being lower than a first priority of the first factor.
6 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
identify a second region of the memory system having one or more second logical addresses associated with the discontinuous corresponding physical addresses; and
suppress rearranging information stored within the discontinuous corresponding physical addresses associated with the second region in response to determining that a write amplify factor fails to satisfy a second threshold.
7 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
determine whether a read count for the region satisfies a second threshold in response to identifying the region, wherein the information is rearranged in response to determining that the read count satisfies the second threshold.
8 . The memory system of claim 1 , wherein, to rearrange the information, the processing circuitry is configured to cause the memory system to:
read data associated with a plurality of physical addresses that comprise the discontinuous corresponding physical addresses; and
write the data associated with the plurality of physical addresses to a second region of the memory system having the one or more logical addresses associated with continuous corresponding physical addresses of the plurality of physical addresses in response to reading the data, wherein the information is rearranged in response to reading the data and writing the data.
9 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
store a first physical address in a logical-to-physical table of the memory system in response to rearranging the information.
10 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
store an indicator, in a logical-to-physical table of the memory system, that the information stored within the discontinuous corresponding physical addresses is rearranged to be within the continuous physical addresses in response to rearranging the information.
11 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
receive a command to access a logical block address in the region; and
load, in a cache associated with a logical-to-physical table, a representation of the logical-to-physical table for the region in response to receiving the command, wherein the representation includes a first physical address and excludes additional physical addresses of the continuous physical addresses corresponding to the region.
12 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
determine whether the region having the one or more logical addresses associated with the discontinuous corresponding physical addresses is occupied in response to identifying the region; and
select the region in response to determining that the region is occupied, wherein the information is rearranged in response to selecting the region.
13 . A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
identify, within the memory system, a region having one or more logical addresses associated with discontinuous corresponding physical addresses in response to a quantity of the one or more logical addresses associated with the discontinuous corresponding physical addresses satisfying a first threshold; and
rearrange, in accordance with a value of a write amplify factor associated with the region of the memory system failing to satisfy a second threshold, information stored within the discontinuous corresponding physical addresses to be within continuous physical addresses of the memory system.
14 . The memory system of claim 13 , wherein the processing circuitry is further configured to cause the memory system to:
record the value of the write amplify factor, wherein the region is identified in response to the value of the write amplify factor failing to satisfy the second threshold.
15 . The memory system of claim 14 , wherein the processing circuitry is further configured to cause the memory system to:
set the first threshold in accordance with the value of the write amplify factor.
16 . The memory system of claim 13 , wherein the processing circuitry is further configured to cause the memory system to:
identify a second region of the memory system having one or more second logical addresses associated with the discontinuous corresponding physical addresses; and
suppress rearranging information stored within the discontinuous corresponding physical addresses associated with the second region in response to determining that a second write amplify factor associated with the second region fails to satisfy a third threshold.
17 . A method, comprising:
identifying, within a memory system, a region having one or more logical addresses associated with discontinuous corresponding physical addresses in response to a quantity of the one or more logical addresses associated with the discontinuous corresponding physical addresses satisfying a threshold; and
rearranging, during a period of inactivity of access operations associated with the memory system, information stored within the discontinuous corresponding physical addresses to be within continuous physical addresses of the memory system.
18 . The method of claim 17 , further comprising:
recording a value of each factor of a plurality of factors associated with the region of the memory system, the plurality of factors including the quantity of the one or more logical addresses, wherein the region is identified in response to the value of one or more factors of the plurality of factors satisfying one or more corresponding thresholds.
19 . The method of claim 18 , wherein the plurality of factors further comprise a write amplify factor associated with the region, a read count for the region, or both.
20 . The method of claim 19 , further comprising:
setting a first threshold for a first factor of the plurality of factors in accordance with the value of the write amplify factor.