Power management integrated circuit and its driving method
The present disclosure relates to a power management integrated circuit and a gate clock modulation circuit, the power management integrated circuit including a delay circuit configured to delay, by a preset time, and output an on clock signal for setting an output start time point of a gate driving circuit and an off clock signal for setting an initialization time point of the gate driving circuit; a multiplexer configured to select and output one among delayed signals transferred through signal lines which are connected to the delay circuit; and a gate clock generation circuit configured to generate a gate clock signal by using the on clock signal and the off clock signal outputted from the multiplexer.
1 . A power management integrated circuit which is connected to a timing controller transmitting first to third clock signals through only three first signal lines and connected to a gate driving circuit receiving gate driving signals through second signal lines more than the number of the first signal lines, comprising:
a logic combination circuit configured to generate the gate driving signals for the gate driving circuit based on the first to third clock signals input from the timing controller through the only three first signal lines,
wherein the logic combination circuit includes:
a logic circuit configured to output a gate start signal and a gate reset signal based on the first to third clock signals to the gate driving circuit through separate logic operations;
a gate clock generating circuit configured to generate the gate clock signals by performing logical operations on the first to third clock signals transferred from the logic circuit,
a delay circuit configured to receive the first to third clock signals, at least one of the first to third clock signals including one pulse transferring in one or more time intervals, to delay and to output the second clock signal or the third clock signal; and
a multiplexer connected to the delay circuit,
wherein the delay circuit is configured to output a plurality of delayed signals on the second clock signal or the third clock signal with different delay times to the multiplexer through a plurality of signal lines,
wherein the delay circuit has more output signal lines than input signal lines,
wherein the multiplexer is configured to randomly select one among the plurality of delayed signals outputted from the delay circuit by receiving a multiplexer control signal and output the selected one to the gate clock generating circuit to generate clock signals,
wherein the first clock signal is a start clock signal, the second clock signal is to set an output start time point of the gate driving circuit, and the third clock signal is to set an initialization time point of the gate driving circuit,
wherein the power management integrated circuit is configured to provide a power to the timing controller and the gate driving circuit, and form the predetermined signal lines with the timing controller as the number of clock signals transferred from the timing controller to the power management integrated circuit,
wherein the gate driving circuit comprises a gate output stage circuit including a plurality of gate output stages to which are sequentially connected, the plurality of gate output stages including at least one gate output stage which drives a dummy logic,
wherein a first gate output stage is configured to receive a gate start signal to determine a start time point of gate driving and a gate reset signal to determine an end time point or an initialization time point of the gate driving, transfer a gate driving volage to a gate line which is connected to an output terminal of the first gate output stage and determine an output time point of the gate driving circuit based on a first gate clock signal,
wherein other gate output stages are configured to receive a gate reset signal to determine an end time point or an initialization time point of the gate driving, transfer a gate driving volage to a gate line which is connected to an output terminal of a corresponding gate output stage and determine an output time point of the gate driving circuit based on a corresponding gate clock signal based on the second clock signal and the third clock signal,
wherein a gate driving voltage of a previous gate output stage used for a gate start signal of a next gate output stage as a gate start signal,
wherein the gate clock modulation circuit is connected to one of an input terminal or an output terminal of the gate clock generation circuit to randomly change the timing of the second and third clock signals generated and transferred by a timing controller,
wherein the gate clock modulation circuit is configured to control a pulse width and a pulse interval of each pulse of the respective gate clock signals and each of the gate clock signals by changing at least one of a rising timing or a falling timing of each pulse of the respective gate clock signals, and
wherein the gate clock modulation circuit is configured to input and output signals in parallel through a plurality of signal modulation lines in order for modulation of gate clock signals.
2 . The power management integrated circuit according to claim 1 , further comprising:
a level shifter configured to receive an output signal outputted from the multiplexer and to adjust the level of the gate clock signal.
3 . The power management integrated circuit according to claim 1 , wherein the gate output stage circuit is configured to receive the output signal of the multiplexer, which is randomly selected.
4 . A display device, comprising:
a timing controller configured to transmit first to third clock signals;
a gate driving unit configured to receive gate driving signals through second signal lines more than the number of the first three signal lines; and
a power management integrated circuit configured to provide a power to the timing controller and the gate driving circuit, and form first signal lines with the timing controller as the number of clock signals transferred from the timing controller to the power management integrated circuit,
wherein the power management integrated circuit includes:
a gate clock generation circuit configured to receive an on clock signal and an off clock signal, among the on and off clock signals, including a plurality of pulses and to generate a gate clock signal by using a rising timing of a pulse of the on clock signal and a falling timing of a pulse of the off clock signal;
a gate clock modulation circuit connected to the gate clock generation circuit and configured to change the rising timing or the falling timing of a pulse of the gate clock signal,
wherein the gate clock modulation circuit includes a delay circuit configured to delay and output the on and off clock signals,
wherein the delay circuit is configured to receive the first to third clock signals, and at least one of the first to third clock signals includes one pulse transferring in one or more time interval intervals,
wherein the delay circuit is configured to output a plurality of delayed signals on the second clock signal or the third clock signal to the multiplexer in different delay times through a plurality of signal lines,
wherein the delay circuit has more output signal lines than input signal lines,
wherein the multiplexer is configured to randomly select one among the plurality of delayed signals outputted from the delay circuit by receiving a multiplexer control signal and output the selected one to the gate clock generating circuit to generate clock signals, and
wherein the first to third clock signals include a start clock signal, the on clock signal for setting an output start time point of a gate driving circuit and the off clock signal for setting an initialization time point of the gate driving circuit, and
wherein the power management integrated circuit is configured to provide a power to a timing controller and the gate driving circuit, and form signal lines with the timing controller as the number of clock signals transferred from the timing controller to the power management integrated circuit,
wherein the gate driving circuit comprises a gate output stage circuit including a plurality of gate output stages to which are sequentially connected, the plurality of gate output stages including at least one gate output stage which drives a dummy logic,
wherein a first gate output stage is configured to receive a gate start signal to determine a start time point of gate driving and a gate reset signal to determine an end time point or an initialization time point of the gate driving, transfer a gate driving volage to a gate line which is connected to an output terminal of the first gate output stage and determine an output time point of the gate driving circuit based on a first gate clock signal,
wherein other gate output stages are configured to receive a gate reset signal to determine an end time point or an initialization time point of the gate driving, transfer a gate driving volage to a gate line which is connected to an output terminal of a corresponding gate output stage and determine an output time point of the gate driving circuit based on a corresponding gate clock signal based on the on clock signal and the off clock signal,
wherein a gate driving voltage of a previous gate output stage is used for a gate start signal of a next gate output stage as a gate start signal,
wherein the gate clock modulation circuit is connected to one of an input terminal or an output terminal of the gate clock generation circuit to randomly change the timing of the second and third clock signals generated and transferred by the timing controller,
wherein the gate clock modulation circuit is configured to control a pulse width and a pulse interval of each pulse of the respective gate clock signals and each of the gate clock signals by changing at least one of a rising timing or a falling timing of each pulse of the respective gate clock signals, and
wherein the gate clock modulation circuit is configured to input and output signals in parallel through a plurality of signal modulation lines in order for modulation of gate clock signals.
5 . The display device according to claim 4 , wherein the gate clock modulation circuit is connected to an input terminal of the gate clock generation circuit and is configured to randomly change the rising timing of the pulse of the on clock signal or the falling timing of the pulse of the off clock signal.
6 . The display device according to claim 4 , wherein the gate clock modulation circuit includes the plurality of signal lines for changing the timing of an input signal and is configured to change the timing of the input signal by randomly connecting one of the signal lines to a port which receives the on clock signal or the off clock signal.
7 . The display device according to claim 4 , wherein the gate clock modulation circuit is disposed between the timing controller and the gate clock generation circuit and is connected to at least one of an on clock signal line for transferring the on clock signal from the timing controller and an off clock signal line for transferring the off clock signal from the timing controller.
8 . The display device according to claim 4 , wherein the gate clock modulation circuit is configured to change the rising timing of the pulse of the gate clock signal according to a preset lookup table.
9 . The display device according to claim 4 , wherein the gate clock generation circuit is configured to generate a plurality of gate clock signals repeatedly with a preset cycle and the gate clock modulation circuit separately modulates the rising timings or the falling timings of the plurality of gate clock signals.
10 . The display device according to claim 4 , wherein the gate output stage is configured to change frequencies of the gate driving signals in response to the rising timing or falling timing of the pulse of the gate clock signal.