Granted Patent B2

US 12,725,670 · App. 18/727,775 · Granted Sep 1, 2026

Inventors: Jack Zezhong Peng (Chengdu, CN); Ke Wang (Chengdu, CN)

Assignee: Chengdu PBM Technology Ltd

G11C17/16H10B20/25

Abstract

Claims (52)

1 . A high-voltage blocking device (HVBD), wherein the HVBD is applied to a three-dimensional memory, and the three-dimensional memory comprises a bit line decoder array layer, a HVBD layer, and a one-time programmable (OTP) array layer that are sequentially arranged from bottom to top;

metal oxide semiconductor (MOS) bit line selection transistors in the bit line decoder array layer are connected to vertical bit lines of OTP devices in the OTP array layer in a one-to-one corresponding manner through the HVBDs in the HVBD layer; and the HVBD is a vertical MOS transistor;

the HVBD layer comprises a plurality of HVBDs;

a plurality of vertical MOS through-holes are provided on the HVBD layer; the HVBDs are arranged to be in a one-to-one correspondence with the vertical MOS through-holes; the HVBDs are embedded in the HVBD layer through the corresponding vertical MOS through-holes;

the HVBD layer comprises a decoder array connection layer, a gate control layer, and a bit line connection layer that are sequentially arranged from bottom to top; and

the decoder array connection layer, the gate control layer, and the bit line connection layer are each provided with a plurality of MOS through-holes; the MOS through-holes on the decoder array connection layer, the MOS through-holes on the gate control layer, and the MOS through-holes on the bit line connection layer are in a one-to-one correspondence and coaxially arranged; the vertical MOS through-holes comprise the MOS through-holes on the decoder array connection layer, the MOS through-holes on the gate control layer, and the MOS through-holes on the bit line connection layer that are coaxially arranged.

2 . The HVBD according to claim 1 , wherein the HVBD comprises: a MOS channel material region and a drain material region sequentially arranged from bottom to top in the vertical MOS through-hole; the MOS channel material region is embedded in the gate control layer, and the drain material region is embedded in the bit line connection layer;

a bit line pillar connection led out by the MOS selection transistor in the bit line decoder array layer is embedded in the decoder array connection layer; the bit line pillar connection is in contact with a lower surface of the MOS channel material region, and an upper surface of the drain material region is in contact with the vertical bit line of the OTP device in the OTP array layer; an upper surface of the MOS channel material region is in contact with a lower surface of the drain material region, allowing the MOS selection transistor in the bit line decoder array layer to be correspondingly connected to the vertical bit line of the OTP device in the OTP array layer via the HVBD; and

side surfaces of the MOS channel material region and the drain material region are covered with a gate insulating material.

3 . The HVBD according to claim 2 , wherein the HVBD layer further comprises: a source layer;

the source layer is positioned under the gate control layer; and

the source layer is provided with a plurality of MOS through-holes; the MOS through-holes on the decoder array connection layer, the MOS through-holes on the source layer, the MOS through-holes on the gate control layer, and the MOS through-holes on the bit line connection layer are in a one-to-one correspondence and coaxially arranged; the MOS through-hole on the decoder array connection layer, the MOS through-hole on the insulating material layer, the MOS through-hole on the gate control layer, and the MOS through-hole on the bit line connection layer together form one vertical MOS through-hole.

4 . The HVBD according to claim 3 , wherein the HVBD comprises: a source material region, a MOS channel material region, and a drain material region sequentially arranged from bottom to top in the vertical MOS through-hole; the source material region is embedded in the source layer; the MOS channel material region is embedded in the gate control layer; and the drain material region is embedded in the bit line connection layer;

a bit line pillar connection led out by the MOS selection transistor in the bit line decoder array layer is embedded in the decoder array connection layer, and is in contact with a lower surface of the source material region in the HVBD, and an upper surface of the drain material region is in contact with the vertical bit line of the OTP device in the OTP array layer; the source material region, the MOS channel material region, and the drain material region are in contact successively, allowing the MOS selection transistor in the bit line decoder array layer to be correspondingly connected to the vertical bit line of the OTP device in the OTP array layer via the HVBD; and

side surfaces of the source material region, the MOS channel material region, and the drain material region are covered with the gate insulating material.

5 . The HVBD according to claim 4 , wherein a main part of the gate control layer is made of a gate electrode material; and the main part is a region other than the MOS channel material region and the gate insulating material.

6 . The HVBD according to claim 5 , wherein the gate electrode material is made of heavily-doped polysilicon;

the gate insulating material is silicon dioxide;

the source material region is made of heavily-doped n-type polysilicon;

the bit line pillar connection is made of heavily-doped n-type polysilicon;

the MOS channel material region is made of lightly-doped p-type polysilicon; and

the drain material region is made of heavily-doped n-type polysilicon.

7 . A three-dimensional memory, using the HVBD according to claim 1 .

8 . The three-dimensional memory according to claim 7 , wherein the HVBD comprises: a MOS channel material region and a drain material region sequentially arranged from bottom to top in the vertical MOS through-hole; the MOS channel material region is embedded in the gate control layer, and the drain material region is embedded in the bit line connection layer;

a bit line pillar connection led out by the MOS selection transistor in the bit line decoder array layer is embedded in the decoder array connection layer; the bit line pillar connection is in contact with a lower surface of the MOS channel material region, and an upper surface of the drain material region is in contact with the vertical bit line of the OTP device in the OTP array layer; an upper surface of the MOS channel material region is in contact with a lower surface of the drain material region, allowing the MOS selection transistor in the bit line decoder array layer to be correspondingly connected to the vertical bit line of the OTP device in the OTP array layer via the HVBD; and

side surfaces of the MOS channel material region and the drain material region are covered with a gate insulating material.

9 . The three-dimensional memory according to claim 8 , wherein the HVBD layer further comprises: a source layer;

the source layer is positioned under the gate control layer; and

the source layer is provided with a plurality of MOS through-holes; the MOS through-holes on the decoder array connection layer, the MOS through-holes on the source layer, the MOS through-holes on the gate control layer, and the MOS through-holes on the bit line connection layer are in a one-to-one correspondence and coaxially arranged; the MOS through-hole on the decoder array connection layer, the MOS through-hole on the insulating material layer, the MOS through-hole on the gate control layer, and the MOS through-hole on the bit line connection layer together form one vertical MOS through-hole.

10 . The three-dimensional memory according to claim 9 , wherein the HVBD comprises: a source material region, a MOS channel material region, and a drain material region sequentially arranged from bottom to top in the vertical MOS through-hole; the source material region is embedded in the source layer; the MOS channel material region is embedded in the gate control layer; and the drain material region is embedded in the bit line connection layer;

a bit line pillar connection led out by the MOS selection transistor in the bit line decoder array layer is embedded in the decoder array connection layer, and is in contact with a lower surface of the source material region in the HVBD, and an upper surface of the drain material region is in contact with the vertical bit line of the OTP device in the OTP array layer; the source material region, the MOS channel material region, and the drain material region are in contact successively, allowing the MOS selection transistor in the bit line decoder array layer to be correspondingly connected to the vertical bit line of the OTP device in the OTP array layer via the HVBD; and

side surfaces of the source material region, the MOS channel material region, and the drain material region are covered with the gate insulating material.

11 . The three-dimensional memory according to claim 10 , wherein a main part of the gate control layer is made of a gate electrode material; and the main part is a region other than the MOS channel material region and the gate insulating material.

12 . The three-dimensional memory according to claim 11 , wherein the gate electrode material is made of heavily-doped polysilicon;

the gate insulating material is silicon dioxide;

the source material region is made of heavily-doped n-type polysilicon;

the bit line pillar connection is made of heavily-doped n-type polysilicon;

the MOS channel material region is made of lightly-doped p-type polysilicon; and

the drain material region is made of heavily-doped n-type polysilicon.

13 . A preparation method for a three-dimensional memory, comprising:

preparing a bit line decoder array layer;

using an upper surface of the bit line decoder array layer, on which bit line pillar connections led out by metal oxide semiconductor (MOS) selection transistors in the bit line decoder array layer are located, as a decoder array connection layer of a high-voltage blocking device (HVBD), wherein a plurality of bit line pillar connections on the bit line decoder array layer are embedded in vertical MOS through-holes in a one-to-one corresponding manner;

depositing a gate electrode material on the decoder array connection layer to obtain initial gate electrode material regions;

depositing a drain insulating material on the initial gate electrode material regions, to obtain initial drain insulating material regions;

etching MOS through-holes at positions corresponding to the MOS through-holes in the initial gate electrode material regions and the initial drain insulating material regions to obtain gate electrode material regions and drain insulating material regions, wherein the gate electrode material region has a thickness equal to a thickness of a gate control layer, the drain insulating material region has a thickness equal to a thickness of a bit line connection layer, and a projection area of the MOS through-hole is greater than a projection area of the corresponding bit line pillar connection;

uniformly depositing an insulating material on upper surfaces of the drain insulating material regions, sidewalls of the MOS through-holes, and the bottoms of the MOS through-holes; etching the insulating material on the upper surfaces of the drain insulating material regions and the bottoms of the MOS through-holes to form second through-holes surrounded by a gate insulating material, wherein a projection area of the second through-hole is less than or equal to a projection area of the corresponding bit line pillar connection;

filling the second through-holes with a MOS channel material, to obtain initial MOS channel material regions;

setting a drain material at positions corresponding to the drain insulating material regions in the second through-holes, to obtain a drain material region; and connecting an upper surface of the drain material region to vertical bit lines of corresponding one-time programmable (OTP) devices in a OTP array layer prepared subsequently, to obtain a three-dimensional memory.

14 . The preparation method for a three-dimensional memory according to claim 13 , wherein before depositing the gate electrode material on the decoder array connection layer to obtain the initial gate electrode material regions, the preparation method further comprises:

depositing a source layer insulating material on the decoder array connection layer to obtain initial source insulating material regions.

15 . The preparation method for a three-dimensional memory according to claim 14 , wherein after depositing the source layer insulating material on the decoder array connection layer to obtain the initial source insulating material regions, the preparation method further comprises:

etching MOS through-holes at positions corresponding to the MOS through-holes on the initial source insulating material regions, the initial gate electrode material regions, and the initial drain insulating material regions to obtain source insulating material regions, gate electrode material regions, and drain insulating material regions, wherein a projection area of the MOS through-hole is larger than a projection area of the corresponding bit line pillar connection.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (16)