Driver and transmitter
Provided are a driver and a transmitter. The driver includes: an n-type metal-oxide-semiconductor field-effect transistor differential circuit, a p-type metal-oxide-semiconductor field-effect transistor differential circuit and a power supply. Gate electrodes of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and the n-type metal-oxide-semiconductor field-effect transistor differential circuit receive a first level signal. The p-type and n-type metal-oxide-semiconductor field-effect transistor differential circuits convert the first level signal into a second level signal used by an actuator. Drain electrodes of the p-type and n-type metal-oxide-semiconductor field-effect transistor differential circuits output the second level signal.
1 . A driver, comprising: an n-type metal-oxide-semiconductor field-effect transistor differential circuit, a p-type metal-oxide-semiconductor field-effect transistor differential circuit and a power supply, and an auxiliary voltage adjusting circuit,
the power supply is connected to a source electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit, a drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit is connected to a drain electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit, and a source electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit is grounded;
a gate electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and a gate electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit are configured to receive a first level signal, the p-type metal-oxide-semiconductor field-effect transistor differential circuit and the n-type metal-oxide-semiconductor field-effect transistor differential circuit are configured to convert the first level signal into a second level signal used by an actuator; and
the drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and the drain electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit are configured to output the second level signal,
the auxiliary voltage adjusting circuit is connected to the drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and the drain electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit; and
when detecting that the drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and a field-effect transistor in the n-type metal-oxide-semiconductor field-effect transistor differential circuit are in an off state, the auxiliary voltage adjusting circuit provides a common mode voltage and outputs a signal, wherein the signal is obtained by superimposing the second level signal on the common mode voltage,
wherein the n-type metal-oxide-semiconductor field-effect transistor differential circuit comprises: a first n-type metal-oxide-semiconductor field-effect transistor and a second n-type metal-oxide-semiconductor field-effect transistor; and
a gate electrode of the first n-type metal-oxide-semiconductor field-effect transistor is configured to receive a binary least significant bit positive signal in the first level signal, and a gate electrode of the second n-type metal-oxide-semiconductor field-effect transistor is configured to receive a binary least significant bit negative signal in the first level signal.
2 . The driver according to claim 1 , wherein the p-type metal-oxide-semiconductor field-effect transistor differential circuit comprises: a first p-type metal-oxide-semiconductor field effect transistor and a second p-type metal-oxide-semiconductor field effect transistor; and
a gate electrode of the first p-type metal-oxide-semiconductor field-effect transistor is configured to receive a binary most significant bit positive signal in the first level signal, and a gate electrode of the second p-type metal-oxide-semiconductor field-effect transistor is configured to receive a binary most significant bit negative signal in the first level signal.
3 . The driver according to claim 2 , wherein a drain electrode of the first n-type metal-oxide-semiconductor field-effect transistor is connected to a drain electrode of the first p-type metal-oxide-semiconductor field-effect transistor, and a drain electrode of the second n-type metal-oxide-semiconductor field-effect transistor is connected to a drain electrode of the second p-type metal-oxide-semiconductor field-effect transistor;
the drain electrode of the first n-type metal-oxide-semiconductor field-effect transistor and the drain electrode of the first p-type metal-oxide-semiconductor field-effect transistor are jointly configured to output a negative signal of the second level signal; and
the drain electrode of the second n-type metal-oxide-semiconductor field-effect transistor and the drain electrode of the second p-type metal-oxide-semiconductor field-effect transistor are jointly configured to output a positive signal of the second level signal.
4 . The driver according to claim 1 , wherein the auxiliary voltage adjusting circuit comprises: a third p-type metal-oxide-semiconductor field-effect transistor and an integrated digital-to-analog converter; a source electrode of the third p-type metal-oxide-semiconductor field-effect transistor is connected to the power supply;
a gate electrode of the third p-type metal-oxide-semiconductor field-effect transistor is connected to the integrated digital-to-analog converter and configured to receive an adjusting signal outputted by the integrated digital-to-analog converter; and
the third p-type metal-oxide-semiconductor field-effect transistor is configured to generate the common mode voltage based on the adjusting signal.
5 . The driver according to claim 4 , wherein the auxiliary voltage adjusting circuit further comprises: a first impedance matching resistor and a second impedance matching resistor;
a first end of the first impedance matching resistor and a first end of the second impedance matching resistor are both connected to a drain electrode of the third p-type metal-oxide-semiconductor field-effect transistor; and
a second end of the first impedance matching resistor is connected to a drain electrode of the first n-type metal-oxide-semiconductor field-effect transistor, and the first impedance matching resistor performs impedance matching processing on a signal at the drain electrode of the first n-type metal-oxide-semiconductor field-effect transistor; and
a second end of the second impedance matching resistor is connected to a drain electrode of the second n-type metal-oxide-semiconductor field-effect transistor, and the second impedance matching resistor performs impedance matching processing on a signal at the drain electrode of the second n-type metal-oxide-semiconductor field-effect transistor.
6 . The driver according to claim 5 , wherein a number of the first impedance matching resistor is at least one, and a number of the second impedance matching resistor is at least one.
7 . The driver according to claim 4 , wherein the integrated digital-to-analog converter is an integrated digital-to-analog converter with 5-bit resolution.
8 . A transmitter, comprising a driver, an encoder, an actuator and a control circuit, wherein
the control circuit is respectively connected to the driver, the encoder and the actuator and configured to monitor and adjust the operation states of the driver, the encoder and the actuator;
the encoder is connected to the driver and configured to input a first level signal to the driver;
the driver is configured to convert the first level signal into a second level signal;
the actuator is connected to the driver and configured to receive the second level signal and execute an action corresponding to the second level signal; and
the driver comprises: an n-type metal-oxide-semiconductor field-effect transistor differential circuit, a p-type metal-oxide-semiconductor field-effect transistor differential circuit and a power supply, and an auxiliary voltage adjusting circuit,
the power supply is connected to a source electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit, a drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit is connected to a drain electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit, and a source electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit is grounded,
a gate electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and a gate electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit are configured to receive the first level signal, the p-type metal-oxide-semiconductor field-effect transistor differential circuit and the n-type metal-oxide-semiconductor field-effect transistor differential circuit are configured to convert the first level signal into the second level signal, and
the drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and the drain electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit are configured to output the second level signal,
the auxiliary voltage adjusting circuit is connected to the drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and the drain electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit; and
when detecting that the drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and a field-effect transistor in the n-type metal-oxide-semiconductor field-effect transistor differential circuit are in an off state, the auxiliary voltage adjusting circuit provides a common mode voltage and outputs a signal, wherein the signal is obtained by superimposing the second level signal on the common mode voltage,
wherein the n-type metal-oxide-semiconductor field-effect transistor differential circuit comprises: a first n-type metal-oxide-semiconductor field-effect transistor and a second n-type metal-oxide-semiconductor field-effect transistor; and
a gate electrode of the first n-type metal-oxide-semiconductor field-effect transistor is configured to receive a binary least significant bit positive signal in the first level signal, and a gate electrode of the second n-type metal-oxide-semiconductor field-effect transistor is configured to receive a binary least significant bit negative signal in the first level signal.
9 . The transmitter according to claim 8 , wherein the p-type metal-oxide-semiconductor field-effect transistor differential circuit comprises: a first p-type metal-oxide-semiconductor field effect transistor and a second p-type metal-oxide-semiconductor field effect transistor; and
a gate electrode of the first p-type metal-oxide-semiconductor field-effect transistor is configured to receive a binary most significant bit positive signal in the first level signal, and a gate electrode of the second p-type metal-oxide-semiconductor field-effect transistor is configured to receive a binary most significant bit negative signal in the first level signal.
10 . The transmitter according to claim 9 , wherein a drain electrode of the first n-type metal-oxide-semiconductor field-effect transistor is connected to a drain electrode of the first p-type metal-oxide-semiconductor field-effect transistor, and a drain electrode of the second n-type metal-oxide-semiconductor field-effect transistor is connected to a drain electrode of the second p-type metal-oxide-semiconductor field-effect transistor;
the drain electrode of the first n-type metal-oxide-semiconductor field-effect transistor and the drain electrode of the first p-type metal-oxide-semiconductor field-effect transistor are jointly configured to output a negative signal of the second level signal; and
the drain electrode of the second n-type metal-oxide-semiconductor field-effect transistor and the drain electrode of the second p-type metal-oxide-semiconductor field-effect transistor are jointly configured to output a positive signal of the second level signal.
11 . The transmitter according to claim 8 , wherein the auxiliary voltage adjusting circuit comprises: a third p-type metal-oxide-semiconductor field-effect transistor and an integrated digital-to-analog converter; a source electrode of the third p-type metal-oxide-semiconductor field-effect transistor is connected to the power supply;
a gate electrode of the third p-type metal-oxide-semiconductor field-effect transistor is connected to the integrated digital-to-analog converter and configured to receive an adjusting signal outputted by the integrated digital-to-analog converter; and
the third p-type metal-oxide-semiconductor field-effect transistor is configured to generate the common mode voltage based on the adjusting signal.
12 . The transmitter according to claim 11 , wherein the auxiliary voltage adjusting circuit further comprises: a first impedance matching resistor and a second impedance matching resistor;
a first end of the first impedance matching resistor and a first end of the second impedance matching resistor are both connected to a drain electrode of the third p-type metal-oxide-semiconductor field-effect transistor; and
a second end of the first impedance matching resistor is connected to a drain electrode of the first n-type metal-oxide-semiconductor field-effect transistor, and the first impedance matching resistor performs impedance matching processing on a signal at the drain electrode of the first n-type metal-oxide-semiconductor field-effect transistor; and
a second end of the second impedance matching resistor is connected to a drain electrode of the second n-type metal-oxide-semiconductor field-effect transistor, and the second impedance matching resistor performs impedance matching processing on a signal at the drain electrode of the second n-type metal-oxide-semiconductor field-effect transistor.
13 . The transmitter according to claim 12 , wherein a number of the first impedance matching resistor is at least one, and a number of the second impedance matching resistor is at least one.
14 . The driver according to claim 11 , wherein the integrated digital-to-analog converter is an integrated digital-to-analog converter with 5-bit resolution.
15 . A data interface circuit, comprising a driver, wherein the driver comprises: an n-type metal-oxide-semiconductor field-effect transistor differential circuit, a p-type metal-oxide-semiconductor field-effect transistor differential circuit and a power supply, and an auxiliary voltage adjusting circuit,
the power supply is connected to a source electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit, a drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit is connected to a drain electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit, and a source electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit is grounded,
a gate electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and a gate electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit are configured to receive the first level signal, the p-type metal-oxide-semiconductor field-effect transistor differential circuit and the n-type metal-oxide-semiconductor field-effect transistor differential circuit are configured to convert the first level signal into the second level signal, and
the drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and the drain electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit are configured to output the second level signal,
the auxiliary voltage adjusting circuit is connected to the drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and the drain electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit; and
when detecting that the drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and a field-effect transistor in the n-type metal-oxide-semiconductor field-effect transistor differential circuit are in an off state, the auxiliary voltage adjusting circuit provides a common mode voltage and outputs a signal, wherein the signal is obtained by superimposing the second level signal on the common mode voltage,
wherein the n-type metal-oxide-semiconductor field-effect transistor differential circuit comprises: a first n-type metal-oxide-semiconductor field-effect transistor and a second n-type metal-oxide-semiconductor field-effect transistor; and
a gate electrode of the first n-type metal-oxide-semiconductor field-effect transistor is configured to receive a binary least significant bit positive signal in the first level signal, and a gate electrode of the second n-type metal-oxide-semiconductor field-effect transistor is configured to receive a binary least significant bit negative signal in the first level signal.