Granted Patent B2

US 12,726,209 · App. 18/658,789 · Granted Sep 1, 2026

Inventors: Hyuk Sun (Burlington, MA); Gil Engel (Lexington, MA); Steven C. Rose (Woburn, MA); Paul S. Wilkins (Weston, MA); Kenneth A. Lawas (Kensington, NH); Bing Zhao (Englewood, CO); Andrew Porter Lewine (Andover, MA); Diane Marie Sutyak (Somerville, MA)

Assignee: Analog Devices, Inc.

H03M1/1014

Abstract

Claims (64)

1 . A digital-to-analog converter (DAC) calibration system for calibrating N DAC cells in a DAC, where N is an integer number of DAC cells greater than 2, the DAC calibration system comprising:

a processor, configured to:

configure the DAC to generate N reference outputs;

configure the DAC to generate N calibration outputs, wherein at least one of the N calibration outputs is generated by two or more of the DAC cells;

determine N overall error values corresponding to a difference between respective individual ones of the N calibration outputs and the N reference outputs; and

determine, using the N overall error values, a cell error value for each of the N DAC cells.

2 . The DAC calibration system of claim 1 , comprising:

a reference cell, configured to provide a specified reference weight value, wherein the reference cell generates the N reference outputs; and

wherein the N overall error values correspond to a difference between respective individual ones of the N calibration outputs and the specified reference weight value.

3 . The DAC calibration system of claim 2 , wherein:

each of the N calibration outputs are generated using a distinct combination of DAC cells, wherein each of the N DAC cells are used in at least one of the N calibration outputs.

4 . The DAC calibration system of claim 3 , wherein:

each of the N calibration outputs of the DAC are configured to have a same weight value, wherein the weight value of each of the N calibration outputs are configured to match the reference weight value.

5 . The DAC calibration system of claim 4 , wherein:

the overall error value of a calibration output corresponds to a sum of the cell error values for the DAC cells that are used to generate the calibration output.

6 . The DAC calibration system of claim 4 , wherein:

each of the N overall error values and the cell error values making up the corresponding ones of the N overall error values comprise a linear equation; and

determining the cell error value for each of the N DAC cells includes solving a system of N linear equations.

7 . The DAC calibration system of claim 6 , wherein:

the DAC cells comprising the N calibration outputs form N row vectors;

the N row vectors form a square matrix;

the N overall error values form an overall error column vector;

determining the cell error value for each of the N DAC cells includes multiplying an inverse of the square matrix by the overall error column vector to generate a cell error column vector; and

wherein respective values in the cell error column vector correspond to respective cell error values.

8 . The DAC calibration system of claim 2 , comprising:

a comparator, configured to compare the reference cell output to a calibration output of the DAC; and

adjustment circuitry, configured to adjust at least one of the reference weight value or a weight value of a DAC cell.

9 . The DAC calibration system of claim 8 , wherein the processor is configured to determine the N overall error values by:

adjusting the adjustment circuitry until an adjustment value at which a state of the comparator changes is found.

10 . The DAC calibration system of claim 9 , wherein:

the processor adjusts the adjustment circuitry using a binary search algorithm.

11 . The DAC calibration system of claim 2 , wherein the processor is configured to:

determine a second cell error value for each of the N DAC cells using a second set of N calibration outputs, wherein the second set of N calibration outputs are generated using a second set of combinations of DAC cells that are distinct from a first set of combinations of DAC cells used for generating the N calibration outputs; and

determine an updated cell error value for each of the N DAC cells using the cell error value and the second cell error value.

12 . The DAC calibration system of claim 11 , wherein:

to determine an updated cell error value includes determining a central tendency of the second cell error value and the cell error value.

13 . The DAC calibration system of claim 1 , wherein the processor is configured to:

adjust each of the N DAC cells based on the determined respective cell error values.

14 . A method of calibrating N digital-to-analog converter (DAC) cells in a DAC, where N is an integer number of DAC cells greater than 2, the method comprising:

generating N calibration outputs using the DAC, wherein at least one of the N calibration outputs is generated by two or more of the DAC cells;

generating N reference outputs using the DAC;

determining N overall error values corresponding to a difference between respective individual ones of the N calibration outputs and the N reference outputs; and

determining, using the N overall error values, a cell error value for each of the N DAC cells.

15 . The method of claim 14 , comprising:

generating each of the N calibration outputs using a distinct combination of DAC cells; and

using each of the N DAC cells in at least one of the N calibration outputs, wherein individual ones of the N reference outputs are configured to have a specified reference weight value.

16 . The method of claim 15 , comprising:

describing each of the distinct combinations of DAC cells as a vector;

generating a square matrix comprising N distinct vectors; and

generating an error vector including the N overall error values.

17 . The method of claim 16 , comprising:

generating a solution vector including the cell error value for each of the N DAC cells by:

inverting the square matrix; and

multiplying an inverse of the square matrix by the error vector to generate the solution vector.

18 . The method of claim 17 , comprising:

pre-selecting the distinct combinations of DAC cells such that a resulting square matrix is invertible.

19 . The method of claim 14 , comprising:

adjusting each of the N DAC cells based on the determined respective cell error values.

20 . A digital-to-analog converter (DAC) calibration system for calibrating N DAC cells in a DAC, where N is an integer number of DAC cells greater than 2, the DAC calibration system comprising:

a processor, configured to:

configure the DAC to generate N reference outputs;

configure the DAC to generate N calibration outputs;

determine N overall error values corresponding to a difference between respective individual ones of the N calibration outputs and the N reference outputs, wherein respective groups comprised of corresponding ones of the N reference outputs and N calibration outputs are generated using a distinct combination of DAC cells, wherein each of the N DAC cells are used in at least one of the N reference outputs or the N calibration outputs; and

determine, using the N overall error values, a cell error value for each of the N DAC cells.

Assignments (1)

Continuity (1)

References Cited (33)