Read-only memory device and method
View Patent ↗A read-only memory (ROM) device includes a complementary field effect transistor (CFET) device which has a first semiconductor device of a first type, and a second semiconductor device of a second type different from the first type. The second semiconductor device is over or under the first semiconductor device. A first word line is electrically coupled to a gate of the first semiconductor device. A second word line is electrically coupled to a gate of the second semiconductor device. At least one bit line is electrically coupled to at least one of a first source/drain of the first semiconductor device, or a first source/drain of the second semiconductor device.
1 . A read-only memory (ROM) device, comprising:
a complementary field effect transistor (CFET) device comprising:
a first semiconductor device of a first type; and
a second semiconductor device of a second type different from the first type, the second semiconductor device over or under the first semiconductor device;
a first word line electrically coupled to a gate of the first semiconductor device;
a second word line electrically coupled to a gate of the second semiconductor device; and
at least one bit line electrically coupled to at least one of
a first source/drain of the first semiconductor device, or
a first source/drain of the second semiconductor device,
wherein
the first semiconductor device is configured to store a first logic value, and
the second semiconductor device is configured to store a second logic value, independently of the first logic value stored in the first semiconductor device.
2 . The ROM device of claim 1 , wherein
the first logic value and the second logic value are the same logic value.
3 . The ROM device of claim 1 , wherein
the first logic value and the second logic value are different logic values.
4 . The ROM device of claim 1 , wherein
the at least one bit line comprises a bit line electrically coupled to both the first source/drain of the first semiconductor device and the first source/drain of the second semiconductor device.
5 . The ROM device of claim 4 , further comprising:
a first power rail configured to carry a first power supply voltage; and
a second power rail configured to carry a second power supply voltage different from the first power supply voltage,
wherein
an electrical connection between the first power rail and a second source/drain of the first semiconductor device corresponds to the first logic value stored in the first semiconductor device, and
an electrical disconnection between the second power rail and a second source/drain of the second semiconductor device corresponds to the second logic value stored in the second semiconductor device, wherein the second logic value is the same as the first logic value.
6 . The ROM device of claim 4 , further comprising:
a first power rail configured to carry a first power supply voltage; and
a second power rail configured to carry a second power supply voltage different from the first power supply voltage,
wherein
an electrical disconnection between the first power rail and a second source/drain of the first semiconductor device corresponds to the first logic value stored in the first semiconductor device, and
an electrical disconnection between the second power rail and a second source/drain of the second semiconductor device corresponds to the second logic value stored in the second semiconductor device, wherein the second logic value is different from the first logic value.
7 . The ROM device of claim 4 , further comprising:
a first power rail configured to carry a first power supply voltage; and
a second power rail configured to carry a second power supply voltage different from the first power supply voltage,
wherein
an electrical connection between the first power rail and a second source/drain of the first semiconductor device corresponds to the first logic value stored in the first semiconductor device, and
an electrical connection between the second power rail and a second source/drain of the second semiconductor device corresponds to the second logic value stored in the second semiconductor device, wherein the second logic value is different from the first logic value.
8 . The ROM device of claim 4 , further comprising:
a first power rail configured to carry a first power supply voltage; and
a second power rail configured to carry a second power supply voltage different from the first power supply voltage,
wherein
an electrical disconnection between the first power rail and a second source/drain of the first semiconductor device corresponds to the first logic value stored in the first semiconductor device, and
an electrical connection between the second power rail and a second source/drain of the second semiconductor device corresponds to the second logic value stored in the second semiconductor device, wherein the second logic value is the same as the first logic value.
9 . A read-only memory (ROM) device, comprising:
a complementary field effect transistor (CFET) device comprising:
a first semiconductor device of a first type; and
a second semiconductor device of a second type different from the first type, the second semiconductor device under the first semiconductor device;
a first word line electrically coupled to a gate of the first semiconductor device;
a second word line electrically coupled to a gate of the second semiconductor device; and
a bit line electrically coupled to both a first source/drain of the first semiconductor device and a first source/drain of the second semiconductor device,
wherein a second source/drain of the first semiconductor device and a second source/drain of the second semiconductor device are electrically disconnected from each other.
10 . The ROM device of claim 9 , further comprising:
a first power rail configured to carry a first power supply voltage; and
a second power rail configured to carry a second power supply voltage different from the first power supply voltage.
11 . The ROM device of claim 10 , wherein
the first power rail is electrically disconnected from the second source/drain of the first semiconductor device, corresponding to a first logic value stored in the first semiconductor device, and
the second power rail is electrically coupled to the second source/drain of the second semiconductor device, corresponding to the first logic value stored in the second semiconductor device.
12 . The ROM device of claim 10 , wherein
the first power rail is electrically disconnected from the second source/drain of the first semiconductor device, corresponding to a first logic value stored in the first semiconductor device, and
the second power rail is electrically disconnected from the second source/drain of the second semiconductor device, corresponding to a second logic value stored in the second semiconductor device, the second logic value different from the first logic value.
13 . The ROM device of claim 10 , wherein
the first power rail is electrically coupled to the second source/drain of the first semiconductor device, corresponding to a first logic value stored in the first semiconductor device, and
the second power rail is electrically coupled to the second source/drain of the second semiconductor device, corresponding to a second logic value stored in the second semiconductor device, the second logic value different from the first logic value.
14 . The ROM device of claim 10 , wherein
the first power rail is electrically coupled to the second source/drain of the first semiconductor device, corresponding to a first logic value stored in the first semiconductor device, and
the second power rail is electrically disconnected from the second source/drain of the second semiconductor device, corresponding to the first logic value stored in the second semiconductor device.
15 . The ROM device of claim 10 , wherein
the CFET device further comprises a local interconnect electrically coupling the first source/drain of the first semiconductor device to the first source/drain of the second semiconductor device.
16 . The ROM device of claim 15 , wherein
the first word line and the first power rail are over the CFET device,
the second word line and the second power rail are under the CFET device, and
the bit line is under and electrically coupled to the local interconnect.
17 . A read-only memory (ROM) device, comprising:
a first complementary field effect transistor (CFET) device comprising:
a first semiconductor device of a first type; and
a second semiconductor device of a second type different from the first type, the second semiconductor device under or over the first semiconductor device;
a first word line electrically coupled to a gate of the first semiconductor device;
a first power rail electrically coupled to a first source/drain of the first semiconductor device;
a first bit line electrically coupled to a second source/drain of the first semiconductor device;
a second word line electrically coupled to a gate of the second semiconductor device;
a second power rail electrically coupled to a first source/drain of the second semiconductor device; and
a second bit line electrically coupled to a second source/drain of the second semiconductor device.
18 . The ROM device of claim 17 , further comprising:
a second CFET device comprising:
a first semiconductor device of the first type; and
a second semiconductor device of the second type, and under or over the first semiconductor device of the second CFET device,
wherein, for the second CFET device,
the first word line is electrically coupled to a gate of the first semiconductor device;
the first power rail is electrically coupled to a first source/drain of the first semiconductor device;
the second bit line is electrically coupled to a second source/drain of the first semiconductor device;
the second word line is electrically coupled to a gate of the second semiconductor device;
the second power rail is electrically coupled to a first source/drain of the second semiconductor device; and
the first bit line is electrically coupled to a second source/drain of the second semiconductor device.
19 . The ROM device of claim 9 , wherein
the first semiconductor device is physically over the second semiconductor device in a thickness direction of the ROM device,
the first source/drain of the first semiconductor device overlaps the first source/drain of the second semiconductor device along the thickness direction, and
the second source/drain of the first semiconductor device overlaps the second source/drain of the second semiconductor device along the thickness direction.
20 . The ROM device of claim 19 , further comprising:
a local interconnect extending between the first semiconductor device and the second semiconductor device along the thickness direction, and electrically coupling the first source/drain of the first semiconductor device to the first source/drain of the second semiconductor device; and
a via structure electrically coupling the local interconnect to the bit line.