Display panel and display apparatus

1 . A display panel, wherein the display panel comprises a pixel driving circuit comprising a driving transistor and a second transistor, wherein a first electrode of the second transistor is connected to a gate of the driving transistor, and a second electrode of the second transistor is connected to a first electrode of the driving transistor, wherein the display panel further comprises:

a base substrate;

a first conductive layer, located on a side of the base substrate, wherein the first conductive layer comprises:

a first conductive portion, configured to form the gate of the driving transistor;

a second active layer, located on a side of the first conductive layer away from the base substrate, wherein the second active layer comprises:

a second active portion, configured to form a channel region of the second transistor; and

an eighth active portion, connected to a side of the second active portion;

a third conductive layer, located on a side of the second active layer away from the base substrate, wherein the third conductive layer comprises:

a first gate line, wherein an orthographic projection of the first gate line on the base substrate extends in a first direction and covers the second active portion, a partial structure of the first gate line is configured to form a top gate of the second transistor, and an orthographic projection of the eighth active portion on the base substrate and an orthographic projection of the first conductive portion on the base substrate are located on both sides of the orthographic projection of the first gate line on the base substrate, respectively;

a dielectric layer, located on a side of the third conductive layer away from the base substrate; and

a fourth conductive layer, located on a side of the dielectric layer away from the base substrate, wherein the fourth conductive layer comprises:

a first bridge portion, connected to the eighth active portion and the first conductive portion through a via hole, respectively;

wherein the first gate line comprises a sixth side edge and a seventh side edge that are arranged opposite to each other and extend in an extension direction of the first gate line, wherein an orthographic projection of at least a partial structure of the sixth side edge on the base substrate is perpendicular to an orthographic projection of the first bridge portion on the base substrate, and an orthographic projection of at least a partial structure of the seventh side edge on the base substrate is perpendicular to the orthographic projection of the first bridge portion on the base substrate.

2 . The display panel according to claim 1 , wherein the sixth side edge comprises a first segment, and the seventh side edge comprises a second segment, wherein an orthographic projection of the first segment on the base substrate is perpendicular to the orthographic projection of the first bridge portion on the base substrate, and an orthographic projection of the second segment on the base substrate is perpendicular to the orthographic projection of the first bridge portion on the base substrate; and

the orthographic projection of the first segment on the base substrate is parallel to the orthographic projection of the second segment on the base substrate, or a straight line where the orthographic projection of the first segment on the base substrate is located intersects with a straight line where the orthographic projection of the second segment on the base substrate is located.

3 . The display panel according to claim 2 , wherein a length of a portion where an orthographic projection of the sixth side edge on the base substrate intersects with the orthographic projection of the first bridge portion on the base substrate is S1, a length of the orthographic projection of the first segment on the base substrate is S2, and a ratio S2/S1 is greater than or equal to 0.7 and less than or equal to 1; and

a length of a portion where an orthographic projection of the seventh side edge on the base substrate intersects with the orthographic projection of the first bridge on the base substrate with a length S3, and a length of the orthographic projection of the second segment on the base substrate is S4, wherein a ratio S4/S3 is greater than or equal to 0.7 and less than or equal to 1.

4 . The display panel according to claim 1 , further comprising:

a second conductive layer, located between the first conductive layer and the second active layer, wherein the second conductive layer comprises:

a second gate line, wherein an orthographic projection of the second gate line on the base substrate extends in the first direction and covers an orthographic projection of the second active portion on the base substrate, and a partial structure of the second gate line is configured to form a bottom gate of the second transistor;

wherein the second gate line comprises a third side edge and a fourth side edge arranged opposite to each other and extending in an extension direction of the second gate line, and the orthographic projection of the first bridge portion on the base substrate perpendicularly intersects with at least part of an orthographic projection of the third side edge on the base substrate and at least part of an orthographic projection of the fourth side edge on the base substrate.

5 . The display panel according to claim 4 , wherein the first gate line comprises a first extension portion, wherein an orthographic projection of the first extension portion on the base substrate is located on the orthographic projection of the first bridge portion on the base substrate, and the first extension portion comprises a first side edge and a second side edge that are arranged opposite to each other and extend in an extension direction of the first extension portion;

the second gate line comprises a second extension portion, wherein an orthographic projection of the second extension portion on the base substrate is located on the orthographic projection of the first bridge portion on the base substrate and overlaps with the orthographic projection of the first extension portion on the base substrate, and the second extension portion comprises the third side edge and the fourth side edge that are arranged opposite to each other and extend in an extension direction of the second extension portion;

the orthographic projection of the third side edge on the base substrate is located on a side of the orthographic projection of the fourth side edge on the base substrate away from the orthographic projection of the first conductive portion on the base substrate;

an orthographic projection of the first side edge on the base substrate is located on a side of an orthographic projection of the second side edge on the base substrate away from the orthographic projection of the first conductive portion on the base substrate;

a distance between an orthographic projection of any first node of the third side edge on the base substrate and the orthographic projection of the first side edge on the base substrate in a second direction is L1, and a distance between the orthographic projection of the first node on the base substrate and the orthographic projection of the fourth side edge on the base substrate in the second direction is L2, wherein the second direction intersects with the first direction, and a ratio L1/L2 is greater than or equal to 0.25 and less than or equal to 0.8; and

a distance between an orthographic projection of any second node of the fourth side edge on the base substrate and the orthographic projection of the second side edge on the base substrate in the second direction is L3, and a distance between the orthographic projection of the second node on the base substrate and the orthographic projection of the third side edge on the base substrate in the second direction is L4, wherein a ratio L3/L4 is greater than or equal to 0.25 and less than or equal to 0.8.

6 . The display panel according to claim 5 , wherein the orthographic projection of the first extension portion on the base substrate covers the orthographic projection of the third side edge on the base substrate, and the orthographic projection of the second extension portion on the base substrate covers the orthographic projection of the second side edge on the base substrate; or

the orthographic projection of the first extension portion on the base substrate covers the orthographic projection of the third side edge on the base substrate and the orthographic projection of the fourth side edge on the base substrate; or

the orthographic projection of the second extension portion on the base substrate covers the orthographic projection of the first side edge on the base substrate and the orthographic projection of the second side edge on the base substrate; or

the orthographic projection of the first extension portion on the base substrate covers the orthographic projection of the fourth side edge on the base substrate, and the orthographic projection of the second extension portion on the base substrate covers the orthographic projection of the first side edge on the base substrate.

7 . The display panel according to claim 5 , wherein a width of an overlapping region of the orthographic projection of the first extension portion on the base substrate and the orthographic projection of the second extension portion on the base substrate in the second direction is L5, wherein a ratio L1/L5 is greater than or equal to 0.6 and less than or equal to 1, and a ratio L3/L5 is greater than or equal to 0.6 and less than or equal to 1;

wherein L1 is greater than or equal to 1.3 μm, and L2 is greater than or equal to 1.3 μm.

8 . The display panel according to claim 5 , wherein the pixel driving circuit comprises a fifth transistor and a sixth transistor, a first electrode of the fifth transistor is connected to a second electrode of the driving transistor, and a first electrode of the sixth transistor is connected to the first electrode of the driving transistor;

wherein the display panel further comprises:

a first active layer, located between the base substrate and the first conductive layer, wherein the first active layer comprises:

a fifth active portion, configured to form a channel region of the fifth transistor; and

a sixth active portion, configured to form a channel region of the sixth transistor;

wherein a distance between the fifth active portion and the sixth active portion in the first direction is L6, a ratio L1/L6 is greater than or equal to 5%, and a ratio L2/L6 is greater than or equal to 5%.

9 . The display panel according to claim 6 , wherein the second gate line comprises the second extension portion, and the orthographic projection of the second extension portion on the base substrate is located on the orthographic projection of the first bridge portion on the base substrate and overlaps with the orthographic projection of the first extension portion on the base substrate;

the orthographic projection of the second extension portion on the base substrate covers the orthographic projection of the first extension portion on the base substrate, the orthographic projection of the second extension portion on the base substrate has a first center line in the first direction, the orthographic projection of the first extension portion on the base substrate has a second center line, and the first center line overlaps with the second center line; and

the orthographic projection of the second extension portion on the base substrate has a first width in the second direction, and the orthographic projection of the first extension portion on the base substrate has a second width in the second direction, wherein the second direction intersects with the first direction;

wherein a ratio of the first width to the second width is 1.5 to 3 at a same position.

10 . The display panel according to claim 6 , wherein the first gate line is provided with a first component and a second component that are connected to each other in the extension direction of the first gate line, a width of an orthographic projection of the first component on the base substrate in the second direction is greater than the width of the orthographic projection of the second component on the base substrate in the second direction, and the second direction intersects with the first direction; and

the second gate line is provided with a third component and a fourth component that are connected to each other in the extension direction of the second gate line, and a width of an orthographic projection of the third component on the base substrate in the second direction is greater than a width of an orthographic projection of the fourth component on the base substrate in the second direction;

wherein the orthographic projection of the first component on the base substrate and the orthographic projection of the third component on the base substrate both cover the orthographic projection of the second active portion on the base substrate, and the orthographic projection of the third component on the base substrate covers the orthographic projection of the first component on the base substrate; and

the orthographic projection of the first bridge portion on the base substrate partially overlaps with the orthographic projection of the first component on the base substrate and the orthographic projection of the second component on the base substrate, and the orthographic projection of the first bridge portion on the base substrate further partially overlaps with the orthographic projection of the third component on the base substrate and the orthographic projection of the fourth component on the base substrate.

11 . The display panel according to claim 6 , wherein the first gate line is provided with a first component and a second component, a width of the first component in the second direction is greater than a width of the second component in the second direction, and the second direction intersects with the first direction; and

the second gate line is provided with a third component and a fourth component, and a width of the third component in the second direction is greater than a width of the fourth component in the second direction;

wherein an orthographic projection of the first component on the base substrate and an orthographic projection of the third component on the base substrate both cover the orthographic projection of the second active portion on the base substrate, and the orthographic projection of the third component on the base substrate covers the orthographic projection of the first component on the base substrate; and

the orthographic projection of the first bridge portion on the base substrate intersects with the orthographic projection of the first component on the base substrate and the orthographic projection of the third component on the base substrate.

12 . The display panel according to claim 1 , wherein the display panel comprises a plurality of pixel driving circuits arranged in an array along the first direction and a second direction, wherein the first direction is a row direction and the second direction is a column direction; and

the pixel driving circuit is configured to drive a light emitting unit to emit light, and further comprises a fourth transistor and a seventh transistor, wherein a first electrode of the fourth transistor is connected to a second electrode of the driving transistor, a gate of the fourth transistor is connected to a third gate line, and a second electrode of the fourth transistor is connected to a data line, and wherein a first electrode of the seventh transistor is connected to a first electrode of the light emitting unit, a second electrode of the seventh transistor is connected to a second initial signal line, and a gate of the seventh transistor is connected to a third reset signal line, and the display panel further comprises:

a first active layer, located between the base substrate and the first conductive layer, wherein the first active layer comprises:

a fourth active portion, configured to form a channel region of the fourth transistor; and

a seventh active portion, configured to form a channel region of the seventh transistor;

wherein the first conductive layer further comprises:

the third gate line, wherein an orthographic projection of the third gate line on the base substrate extends in the first direction and covers an orthographic projection of the fourth active portion on the base substrate, and a partial structure of the third gate line is configured to form the gate of the fourth transistor; and

the third reset signal line, wherein an orthographic projection of the third reset signal line on the base substrate extends in the first direction and covers the seventh active portion, and a partial structure of the third reset signal line is configured to form the gate of the seventh transistor; and

wherein the third gate line of the pixel driving circuit of a current row is multiplexed as the third reset signal line of the pixel driving circuit of a previous row.

13 . The display panel according to claim 1 , wherein the pixel driving circuit further comprises a storage capacitor, a first electrode of the storage capacitor is connected to the gate of the driving transistor, and a second electrode of the storage capacitor is connected to a first power supply line; and

the first conductive portion is further configured to form a first electrode of the storage capacitor;

wherein the display panel further comprises:

a fifth conductive layer, located on a side of the fourth conductive layer away from the base substrate, wherein the fifth conductive layer comprises:

the first power supply line, wherein an orthographic projection of the first power supply line on the base substrate extends in a second direction, and the second direction intersects with the first direction;

a second conductive layer, located between the first conductive layer and the second active layer, wherein the second conductive layer comprises:

a second conductive portion, wherein an orthographic projection of the second conductive portion on the base substrate partially overlaps with the orthographic projection of the first conductive portion on the base substrate, the second conductive portion is configured to form a second electrode of the storage capacitor, and the second conductive portion is connected to the first power supply line through a via hole;

wherein the first direction is a row direction and the second direction is a column direction; wherein

the display panel comprises a plurality of repeating units arranged along the row direction and the column direction, wherein the repeating unit comprises two pixel driving circuits adjacent to each other in the row direction, and each column of the pixel driving circuits is correspondingly provided with one first power supply line and one second conductive portion;

in a same repeating unit, two first power supply lines are connected to each other; and

in the repeating units adjacent in the row direction, adjacent second conductive portions are connected to each other;

wherein in the same repeating unit, two adjacent pixel driving circuits in the row direction are configured as mirror structures to each other.

14 . The display panel according to claim 1 , wherein the pixel driving circuit comprises a fifth transistor, wherein a first electrode of the fifth transistor is connected to a second electrode of the driving transistor, and a second electrode of the fifth transistor is connected to a first power supply line, wherein the display panel further comprises:

a first active layer, located between the base substrate and the first conductive layer, wherein the first active layer comprises:

a fifth active portion, configured to form a channel region of the fifth transistor;

wherein the first conductive layer further comprises:

an enable signal line, wherein an orthographic projection of the enable signal line on the base substrate extends along the first direction and covers the fifth active portion, and a partial structure of the enable signal line is configured to form a gate of the fifth transistor; and

a fifth conductive layer, located on a side of the fourth conductive layer away from the base substrate, wherein the fifth conductive layer comprises:

the first power supply line, wherein an orthographic projection of the first power supply line on the base substrate extends in a second direction, and the second direction intersects with the first direction; and

wherein the fourth conductive layer further comprises:

a second bridge, connected to the second electrode of the fifth transistor through a first via hole and connected to the first power supply line through another via hole;

wherein the first direction is a row direction and the second direction is a column direction;

the display panel comprises a plurality of repeating units arranged along the row direction and the column direction, and the repeating unit comprises two pixel driving circuits adjacent to each other in the row direction; and

the second bridge portion is arranged in one-to-one correspondence with the pixel driving circuit, and in the repeating units adjacent in the row direction, adjacent second bridge portions are connected to each other and share the first via hole.

15 . The display panel according to claim 1 , further comprising:

a fifth conductive layer, located on a side of the fourth conductive layer away from the base substrate, wherein the fifth conductive layer comprises:

a first power supply line, wherein an orthographic projection of the first power supply line on the base substrate extends in a second direction, and the second direction intersects with the first direction; and

wherein the orthographic projection of the first power supply line on the base substrate covers the orthographic projection of the first bridge portion on the base substrate;

wherein a gate of the second transistor is connected to the first gate line, and the second electrode of the second transistor is connected to the first electrode of the driving transistor;

wherein the second active layer further comprises:

a first active portion, configured to form a channel region of a first transistor; and

the second active portion, configured to form the channel region of the second transistor;

wherein the display panel further comprises:

a second conductive layer, located between the first conductive layer and the second active layer, wherein the second conductive layer comprises:

a second gate line, wherein an orthographic projection of the second gate line on the base substrate extends in the first direction and covers an orthographic projection of the second active portion on the base substrate, and a partial structure of the second gate line is configured to form a bottom gate of the second transistor, and the orthographic projection of the first gate line on the base substrate covers the orthographic projection of the second active portion on the base substrate, and the partial structure structure of the first gate line is configured to form the top gate of the second transistor; and

a first reset signal line, wherein an orthographic projection of the first reset signal line on the base substrate extends in the first direction and covers an orthographic projection of the first active portion on the base substrate, and a partial structure of the first reset signal line is configured to form a bottom gate of the first transistor; and

wherein an orthographic projection of the first power supply line on the base substrate covers the orthographic projection of the first active portion on the base substrate and the orthographic projection of the second active portion on the base substrate.

16 . The display panel according to claim 1 , wherein a second electrode of a first transistor is connected to a first initial signal line, and the second electrode of the second transistor is connected to the first electrode of the driving transistor, wherein the pixel driving circuit further comprises a sixth transistor, and a first electrode of the sixth transistor is connected to the first electrode of the driving transistor;

wherein the display panel further comprises:

a second conductive layer, located between the first conductive layer and the second active layer, wherein the second conductive layer comprises:

the first initial signal line, wherein an orthographic projection of the first initial signal line on the base substrate extends in the first direction;

a first active layer, located between the base substrate and the first conductive layer, wherein the first active layer comprises:

a third active portion, configured to form a channel region of the driving transistor;

a sixth active portion, configured to form a channel region of the sixth transistor; and

an eleventh active portion, connected between the third active portion and the sixth active portion;

wherein the second active layer further comprises:

the second active portion, configured to form the channel region of the second transistor;

a ninth active portion, connected between the second active portion and the eighth active portion; and

a fourteenth active portion, connected to a side of the second active portion away from the eighth active portion;

wherein the fourth conductive layer further comprises:

a third bridge portion, connected to the fourteenth active portion and connected to the first initial signal line through a via hole; and

a fourth bridge portion, connected to the eleventh active portion through a via hole and connected to the fourteenth active portion through another via hole;

wherein the display panel comprises a plurality of pixel driving circuits arranged in an array along the first direction and a second direction, wherein the first direction is a row direction and the second direction is a column direction; wherein

the display panel comprises a plurality of repeating units arranged along the row direction and the column direction, and the repeating unit comprises two pixel driving circuits; and

in a same repeating unit, two pixel driving circuits share the third bridge portion.

17 . The display panel according to claim 16 , wherein the pixel driving circuit further comprises a fifth transistor, a sixth transistor and a seventh transistor, wherein a first electrode of the fifth transistor is connected to a second electrode of the driving transistor, a second electrode of the fifth transistor is connected to a first power supply line, a first electrode of the sixth transistor is connected to the first electrode of the driving transistor, and a second electrode of the sixth transistor is connected to a first electrode of the seventh transistor, and wherein the display panel further comprises:

the first active layer, located between the base substrate and the first conductive layer, wherein the first active layer comprises:

a fifth active portion, configured to form a channel region of the fifth transistor;

a sixth active portion, configured to form a channel region of the sixth transistor; and

a seventh active portion, configured to form a channel region of the seventh transistor;

wherein the first conductive layer further comprises:

an enable signal line, wherein an orthographic projection of the enable signal line on the base substrate extends along the first direction and covers the fifth active portion and the sixth active portion, and a partial structure of the enable signal line is configured to form a gate of the fifth transistor and the partial structure structure of the enable signal line is configured to form a gate of the sixth transistor; and

a third reset signal line, wherein an orthographic projection of the third reset signal line on the base substrate extends in the first direction and covers the seventh active portion, and a partial structure of the third reset signal line is configured to form a gate of the seventh transistor;

the second conductive layer, located between the first conductive layer and the second active layer, wherein the second conductive layer comprises:

the first initial signal line, wherein the orthographic projection of the first initial signal line on the base substrate extends in the first direction;

a fifth conductive layer, located on a side of the fourth conductive layer away from the base substrate, wherein the fifth conductive layer comprises:

the first power supply line, wherein an orthographic projection of the first power supply line on the base substrate extends in a second direction, and the second direction intersects with the first direction; and

wherein the fourth conductive layer further comprises:

a second bridge, connected to the second electrode of the fifth transistor through a via hole and connected to the first power supply line through another via hole; and

wherein, in a same pixel driving circuit, the orthographic projection of the first conductive portion on the base substrate is located between the orthographic projection of the enable signal line on the base substrate and the orthographic projection of the first gate line on the base substrate; and

in the same pixel driving circuit, the orthographic projection of the first gate line on the base substrate, the orthographic projection of the third reset signal line on the base substrate and the orthographic projection of the first initial signal line on the base substrate are sequentially arranged in a direction away from the first conductive portion.

18 . The display panel according to claim 17 , wherein a gate of the first transistor is connected to a second reset signal line; and

wherein the second active layer further comprises:

a first active portion, configured to form a channel region of the first transistor;

wherein the display panel further comprises:

the second conductive layer, located between the first conductive layer and the second active layer, wherein the second conductive layer comprises:

a first reset signal line, wherein an orthographic projection of the first reset signal line on the base substrate extends in the first direction and covers an orthographic projection of the first active portion on the base substrate, and a partial structure of the first reset signal line is configured to form a bottom gate of the first transistor;

wherein the third conductive layer further comprises:

a second reset signal line, wherein an orthographic projection of the second reset signal line on the base substrate extends in the first direction and covers the orthographic projection of the first active portion on the base substrate, and a partial structure of the second reset signal line is configured to form a top gate of the first transistor; and

wherein the orthographic projection of the first reset signal line on the base substrate is located between the orthographic projection of the first initial signal line on the base substrate and the orthographic projection of the third reset signal line on the base substrate.

19 . The display panel according to claim 17 , wherein the first direction is a row direction and the second direction is a column direction, and wherein the pixel driving circuit further comprises a fourth transistor, a first electrode of the fourth transistor is connected to the second electrode of the driving transistor, and a second electrode of the fourth transistor is connected to a data signal line; wherein

the fifth conductive layer further comprises:

a data line, wherein an orthographic projection of the data line on the base substrate extends in the second direction; and

the fourth conductive layer further comprises:

a sixth bridge, connected to the data line through a via hole and connected to a second electrode of the fourth transistor through another via hole;

wherein the display panel comprises a plurality of repeating units arranged along the row direction and the column direction, the repeating unit comprises two pixel driving circuits, and each column of the pixel driving circuits is correspondingly provided with one first power supply line and one data line; and

in a same repeating unit, two first power supply lines are connected to each other, and orthographic projections of two data lines on the base substrate are arranged on both sides of the orthographic projections of two first power supply lines on the base substrate, respectively;

wherein the first transistor and the second transistor are N-type transistors, and the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are P-type transistors.

20 . The display panel according to claim 1 , wherein the display panel comprises a plurality of pixel driving circuits arranged in an array along the first direction and a second direction, wherein the first direction is a row direction and the second direction is a column direction, and wherein the display panel comprises a plurality of sub-pixels arranged in an array along the row direction and the column direction, the sub-pixel comprises the pixel driving circuit, and the display panel further comprises:

a fifth conductive layer, located on a side of the fourth conductive layer away from the base substrate, wherein the fifth conductive layer comprises:

a first power supply line, wherein an orthographic projection of the first power supply line on the base substrate extends in the second direction; and

a plurality of virtual pixel rows, wherein the virtual pixel rows are located between two adjacent rows of sub-pixels, the virtual pixel row comprises a plurality of row virtual sub-pixels, and the row virtual sub-pixel comprises a row virtual pixel driving circuit;

wherein the row virtual pixel driving circuit comprises a row virtual transistor and a row virtual signal line, the row virtual transistor and the row virtual signal line are connected to each other into an integral structure, and the integral structure is connected to the first power supply line;

wherein the display panel comprises the plurality of pixel driving circuits arranged in the array along the first direction and the second direction, wherein the first direction is the row direction and the second direction is the column direction, wherein the pixel driving circuit is configured to drive a light emitting unit to emit light, and further comprises a fourth transistor, a sixth transistor and a seventh transistor, wherein a first electrode of the fourth transistor is connected to a second electrode of the driving transistor, a gate of the fourth transistor is connected to a third gate line, and a second electrode of the fourth transistor is connected to a data line, wherein a first electrode of the sixth transistor is connected to the first electrode of the driving transistor, a second electrode of the sixth transistor is connected to a first electrode of the light emitting unit, and wherein a first electrode of the seventh transistor is connected to the first electrode of the light emitting unit, a second electrode of the seventh transistor is connected to a second initial signal line, and a gate of the seventh transistor is connected to a third reset signal line;

wherein an orthographic projection of the seventh transistor in the pixel driving circuit of a current row on the base substrate is located at a side of an orthographic projection of the virtual pixel row on the base substrate away from an orthographic projection of the sixth transistor in the pixel driving circuit of the current row on the base substrate, and the display panel further comprises:

a first active layer, located between the base substrate and the first conductive layer, wherein the first active layer comprises:

a fourth active portion, configured to form a channel region of the fourth transistor;

a sixth active portion, configured to form a channel region of the sixth transistor;

a seventh active portion, configured to form a channel region of the seventh transistor; and

a third conductive portion, at least partially located in a region where the virtual pixel row is located, wherein an orthographic projection of the third conductive portion on the base substrate extends along the second direction, and the third conductive portion is configured to be connected to the second electrode of the sixth transistor in the pixel driving circuit of the current row and the first electrode of the seventh transistor in the pixel driving circuit of the current row;

wherein the first conductive layer further comprises:

the third gate line, wherein an orthographic projection of the third gate line on the base substrate extends in the first direction and covers an orthographic projection of the fourth active portion on the base substrate, and a partial structure of the third gate line is configured to form the gate of the fourth transistor; and

the third reset signal line, wherein an orthographic projection of the third reset signal line on the base substrate extends in the first direction and covers the seventh active portion, and a partial structure of the third reset signal line is configured to form the gate of the seventh transistor; and

wherein the third gate line of the pixel driving circuit of a current row is multiplexed as the third reset signal line of the pixel driving circuit of a previous row;

wherein the row virtual pixel driving circuit further comprises a row virtual storage capacitor, the row virtual signal line comprises a row virtual second initial signal line, a row virtual third reset signal line, a row virtual gate line and a row virtual enable signal line, and the row virtual transistor comprises a row virtual driving transistor and a row virtual fifth transistor, wherein a first notch region is arranged between an orthographic projection of the row virtual fifth transistor on the base substrate and an orthographic projection of the row virtual driving transistor on the base substrate, the orthographic projection of the third conductive portion on the base substrate is located in the first notch region, and an orthographic projection of the second electrode of the row virtual storage capacitor on the base substrate, an orthographic projection of the row virtual second initial signal line on the base substrate, an orthographic projection of the row virtual third reset signal line on the base substrate, and an orthographic projection of the row virtual gate line on the base substrate and an orthographic projection of the row virtual enable signal line on the base substrate are all disconnected at the first notch region;

wherein the third conductive portion is located on the first conductive layer, and the row virtual pixel driving circuit comprises a row virtual first transistor, wherein a first electrode of the row virtual first transistor is connected to a gate of the row virtual driving transistor, a second electrode of the row virtual first transistor is connected to a row virtual first initial signal line, and a gate of the row virtual first transistor is connected to a row virtual second reset signal line; and

the row virtual signal line further comprises the row virtual second reset signal line, wherein the row virtual second reset signal line is located on the third conductive layer, and an orthographic projection of the row virtual second reset signal line on the base substrate extends along the first direction and is located between the first notch region and a region where the pixel driving circuit of the previous row is located;

wherein the display panel further comprises:

a fifth bridge portion, located on the fourth conductive layer, wherein the fifth bridge portion is connected to the third conductive portion and a second electrode of the sixth transistor in the pixel driving circuit in current row through a via hole respectively, and an orthographic projection of the fifth bridge portion on the base substrate intersects with an orthographic projection of the second reset signal line on the base substrate;

wherein the display panel further comprises:

a plurality of virtual pixel columns, wherein the virtual pixel column is located between two adjacent columns of sub-pixels, the virtual pixel column comprises a plurality of column virtual sub-pixels, the column virtual sub-pixel comprises a column virtual pixel driving circuit, the column virtual pixel driving circuit comprises a channel region of a column virtual reset transistor, and an orthographic projection of the channel region of the column virtual reset transistor on the base substrate has a second notch region; and

the first conductive layer further comprises a third reset signal line, wherein an orthographic projection of the third reset signal line on the base substrate extends along the first direction and passes through the second notch region;

wherein the virtual pixel column further comprises a column virtual storage capacitor and a column virtual signal line, wherein a first electrode of the column virtual storage capacitor is connected to the enable signal line, the column virtual signal line and the column virtual transistor are connected to each other into an integral structure, and the integral structure is connected to the first power supply line.