Display device gate wiring and fanout wiring configurations
A display device includes: a substrate including a display area and a non-display area including a pad area; an inorganic insulating layer disposed on the substrate and including a first inorganic insulating layer, a second inorganic insulating layer, and a third inorganic insulating layer; a light-emitting element layer disposed on the inorganic insulating layer and including a light-emitting element overlapping the display area in a plan view; a gate wiring overlapping the display area in the plan view, extending in a first direction and disposed between the first inorganic insulating layer and the second inorganic insulating layer; and a fanout wiring extending in a direction toward the display area from the pad area and disposed between the second inorganic insulating layer and the third inorganic insulating layer, where a sheet resistance of the gate wiring is lower than a sheet resistance of the fanout wiring.
1 . A display device comprising:
a substrate comprising a display area and a non-display area outside the display area, wherein the non-display area comprises
a pad area;
an inorganic insulating layer disposed on the substrate;
a gate wiring overlapping the display area in a plan view, extending in a first direction and disposed inside the inorganic insulating layer;
a fanout wiring extending in a direction toward the display area from the pad area in the plan view, disposed inside the inorganic insulating layer and comprising a different material from a material of the gate wiring;
a light-emitting element layer disposed on the inorganic insulating layer and comprising a light-emitting element overlapping the display area in the plan view;
a sealing substrate disposed on the light-emitting element layer; and
a sealing member disposed between the substrate and the sealing substrate and surrounding the display area in the plan view,
wherein a sheet resistance of the gate wiring is lower than a sheet resistance of the fanout wiring,
wherein the fanout wiring extends while crossing the sealing member in the plan view, and
a melting point of a material included in the fanout wiring is higher than a melting point of a material included in the gate wiring,
wherein the sealing member comprises a laser-curable material, and
wherein the inorganic insulating layer comprises a buffer layer, a first inorganic insulating layer, and a second inorganic insulating layer, which are sequentially stacked one on another, and
the display device further comprises:
a lower metal layer overlapping the display area in the plan view and disposed between the substrate and the buffer layer; and
a semiconductor layer overlapping the lower metal layer in the plan view, disposed between the buffer layer and the first inorganic insulating layer and comprising an oxide semiconductor, and
the fanout wiring is arranged in a same layer as the lower metal layer.
2 . The display device of claim 1 , wherein the sheet resistance of the gate wiring is less than or equal to about a half of the sheet resistance of the fanout wiring.
3 . The display device of claim 1 , wherein
the gate wiring comprises at least one selected from titanium nitride and titanium and aluminum, and
the fanout wiring comprises molybdenum.
4 . The display device of claim 1 , wherein
the gate wiring is disposed between the first inorganic insulating layer and the second inorganic insulating layer, and
the fanout wiring is disposed between the substrate and the buffer layer.
5 . The display device of claim 1 , wherein
the substrate comprises a first edge extending in the first direction and a second edge extending in a second direction crossing the first direction, and
a length of the first edge is greater than a length of the second edge.
6 . The display device of claim 1 , wherein
the fanout wiring comprises adjacent fanout wirings, and
the adjacent fanout wirings are disposed in a same layer as each other.
7 . The display device of claim 1 , further comprising:
an encapsulation layer disposed on the light-emitting element layer and comprising an inorganic encapsulation layer and an organic encapsulation layer.