FFT radar system

1 . A method of signal processing, comprising:

receiving a set of signal samples;

performing a fast Fourier transform (FFT) operation on the set of signal samples to determine a set of FFT values;

variably compressing ones of the FFT values at different levels of compression;

storing the variably compressed ones of the FFT values;

decompressing the variably compressed ones of the FFT values; and

applying windowing to a frame of the decompressed variably compressed ones of the FFT values;

wherein the variably compressing is responsive to an amount of signal attenuation provided by the windowing.

2 . The method of claim 1 and further including, prior to the first step:

transmitting a frequency modulated signal;

detecting a received signal; and

sampling the received signal to produce the set of signal samples.

3 . The method of claim 2 wherein the frequency modulated signal includes an FMCW radar signal.

4 . The method of claim 2 wherein the determining step determines the plurality of FFT values corresponding to a respective digitized value for each sample in a plurality of signal samples from the received signal.

5 . The method of claim 1 , wherein the windowing is selected from a group including a Hann and Blackman windowing.

6 . The method of claim 1 , wherein the determining step includes determining a plurality of range FFT values.

7 . The method of claim 6 , wherein the applying windowing produces selectively attenuated range FFT values, and further including, sixth, determining a plurality of velocity FFT values in response to the selectively attenuated range FFT values.

8 . The method of claim 1 and further including:

receiving a set of signals associated with radar values; and

sampling the set of signals to produce the plurality of signal samples.

9 . The method of claim 1 , wherein the different levels of compression include at least four distinct compression levels, each corresponding to a different range of signal attenuation values.

10 . The method of claim 1 , wherein the different levels of compression include:

a first level of compression of a first percentage for FFT values corresponding to a signal attenuation within a first range;

a second level of compression of a second percentage for FFT values corresponding to a signal attenuation within a second range; and

a third level of compression of a third percentage for FFT values corresponding to a signal attenuation within a third range.

11 . A system, comprising:

fast Fourier transfer (FFT) determining circuitry adapted to produce a plurality of FFT values in response to the plurality of digital samples;

data compression circuitry coupled to the FFT determining circuitry and adapted to variably compress ones of the FFT values at different levels of compression;

data decompression circuitry adapted to decompress the variably compressed ones of the FFT values; and

windowing circuitry adapted to apply windowing to a frame of the decompressed variably compressed ones of the FFT values,

wherein the variably compressing is responsive to an amount of signal attenuation provided by the windowing.

12 . The system of claim 11 , and further including:

analog circuitry adapted to receive a set of analog signals; and

analog-to-digital conversion (ADC) circuitry coupled to the analog circuitry and adapted to produce a plurality of digital samples corresponding to at least one analog signal in the set of analog signals.

13 . The system of claim 12 wherein the FFT determining circuitry is coupled to the ADC circuitry.

14 . The system of claim 13 , wherein the FFT determining circuitry and the data compression circuitry comprise a processor.

15 . The system of claim 14 wherein the processor is integrated in a same chip as the analog circuitry and the ADC circuitry.

16 . The system of claim 14 wherein the processor is a general purpose processor.

17 . The system of claim 12 and further including at least one antenna coupled to the analog circuitry.

18 . The system of claim 12 and further including transmitter circuitry adapted to transmit a set of transmit signals, wherein the set of analog signals are responsive to the set of transmit signals.

19 . The system of claim 11 , further comprising:

analog front-end circuitry; and

analog-to-digital conversion circuitry,

wherein the fast Fourier transfer (FFT) determining circuitry, data compression circuitry, data decompression circuitry, windowing circuitry, the analog front-end circuitry, and the analog-to-digital conversion circuitry are integrated on a single semiconductor substrate.

20 . The system of claim 11 , wherein the data compression circuitry implements bit-resolution reduction from a first number of bits O to a second number of bits L, in which L is less than O, and in which the difference between O and L is based on a chirp index position within a frame of chirps.