Virtual data links
A multi-lane data communication link, such as a PCIe link, may be configured as virtual links. Each virtual link may correspond to a unique subset of the lanes. Data packets provided by multiple virtual machines and associated virtual functions may be buffered in transmit queues. Each transmit queue may correspond to a unique one of the virtual links. The data may be provided from each of the transmit queues to data transmitting circuitry coupled to active lanes.
1 . A method for transferring data over a link having a plurality of active lanes, comprising:
indicating virtual links will be used over the link having the plurality of active lanes with a control register;
identifying a count for a plurality of virtual links to be used over the link with a control register;
identifying a priority level for each virtual link with the control register;
buffering in a plurality of transmit queues data packets provided by each of a plurality of transmitting components, each transmit queue corresponding to one of the plurality of virtual links established in accordance with the control register, each virtual link having a virtual linkwidth equal to a width of active lanes uniquely corresponding to a respective virtual link; and
providing data from each of the transmit queues to data transmitting circuitry coupled to the plurality of active lanes; wherein providing data from each of the transmit queues comprises providing from one of the transmit queues a number of bytes of data equal to a virtual linkwidth of a respective virtual link corresponding to one of the transmit queues before providing data from another of the transmit queues.
2 . The method of claim 1 , wherein:
the link having the plurality of active lanes comprises a Peripheral Component Interconnect Express (PCIe) link configured for Single-Root Input/Output Virtualization (SRIOV);
the plurality of transmitting components comprises a plurality of virtual machines of a host processing system; and
the method further comprises providing the data packets from a virtual function associated with each virtual machine to the plurality of transmit queues.
3 . The method of claim 1 , further comprising each of the transmitting components including a virtual link identifier in a transaction layer packet header, the virtual link identifier identifying one of the virtual links.
4 . The method of claim 1 , further comprising:
receiving data over the plurality of active lanes by data receiving circuitry coupled to the plurality of active lanes; and
providing, by the data receiving circuitry, the data received over the plurality of active lanes to a plurality of receive queues, each receive queue corresponding to one of the transmit queues and corresponding to one of the virtual links, including buffering data packets in the receive queues correspondingly to the buffering of the data packets in the transmit queues, and including providing to one of the receive queues a number of bytes of data equal to a virtual linkwidth of a respective virtual link corresponding to one of the receive queues before providing data to another of the receive queues.
5 . The method of claim 1 , further comprising dynamically changing the virtual linkwidths of a plurality of the virtual links.
6 . The method of claim 1 , wherein at least a first one of the virtual links has a higher virtual linkwidth, and a second one of the virtual links has a lower virtual linkwidth.
7 . The method of claim 6 , wherein:
each of the transmitting components is assigned to a virtual link, where each virtual link has a priority level identified by the control register, a first one of the transmitting components has a higher priority, and a second one of the transmitting components has a lower priority; and
buffering the data packets comprises buffering data packets provided by the first one of the transmitting components in a transmit queue corresponding to the first one of the virtual links and buffering data packets provided by the second one of the transmitting components in a transmit queue corresponding to the second one of the virtual links.
8 . The method of claim 7 , wherein the first one of the transmitting components produces larger data packets, and the second one of the transmitting components produces smaller data packets.
9 . The method of claim 1 , wherein the link consists of the plurality of active lanes and at least one electrically idle lane.
10 . A system for transferring data over a link, comprising:
a control register indicating virtual links will be used over the link having the plurality of active lanes, the control register identifying a count for a plurality of virtual links to be used over the link, and the control register identifying a priority level for each virtual link;
a plurality of transmit queues, each corresponding to one of the plurality of virtual links established in accordance with the control register, each virtual link having a virtual linkwidth equal to a width of active lanes uniquely corresponding to a respective virtual link;
transmit queue routing circuitry configured to buffer in the transmit queues data packets received from a plurality of transmitting components; and
transmit queue reading circuitry configured to provide data from each of the transmit queues to data transmitting circuitry coupled to a plurality of active lanes of the link, the transmit queue reading circuitry is configured to provide from one of the transmit queues a number of bytes of data equal to a virtual linkwidth of a respective virtual link corresponding to one of the transmit queues before providing data from another of the transmit queues.
11 . The system of claim 10 , wherein:
the link having the plurality of active lanes comprises a Peripheral Component Interconnect express (PCIe) link configured for Single-Root Input/Output Virtualization (SRIOV);
the plurality of transmitting components comprises a plurality of virtual machines of a host processing system; and
the transmit queue routing circuitry is configured to transfer the data packets from a virtual function associated with each virtual machine to the plurality of transmit queues.
12 . The system of claim 10 , wherein each of the transmitting components is configured to include a virtual link identifier in a transaction layer packet header, the virtual link identifier identifying one of the virtual links.
13 . The system of claim 10 , further comprising:
a plurality of receive queues, each corresponding to one of the virtual links and corresponding to one of the transmit queues; and
receive queue routing logic configured to buffer data received by data receiving circuitry over the plurality of active lanes in the plurality of receive queues, wherein the receive queue routing logic is configured to provide to one of the receive queues a number of bytes of data equal to a virtual linkwidth of a respective virtual link corresponding to one of the receive queues before providing data to another of the receive queues.
14 . The system of claim 10 , wherein at least a first one of the virtual links has a higher virtual linkwidth, and a second one of the virtual links has a lower virtual linkwidth.
15 . The system of claim 14 , wherein:
each of the transmitting components is assigned to a virtual link, where each virtual link has a priority level identified by the control register, a first one of the transmitting components has a higher priority, and a second one of the transmitting components has a lower priority; and
the receive queue routing logic is configured to buffer the data packets provided by the first one of the transmitting components in one of the transmit queues corresponding to the first one of the virtual links and to buffer data packets provided by the second one of the transmitting components in another of the transmit queues corresponding to the second one of the virtual links.
16 . The system of claim 15 , wherein the first one of the transmitting components is configured to produce larger data packets, and the second one of the transmitting components is configured to produce smaller data packets.
17 . The system of claim 10 , wherein the link consists of the plurality of active lanes and at least one electrically idle lane.
18 . A system for transferring data over a Peripheral Component Interconnect Express (PCIe) link, comprising:
a control register indicating virtual links will be used over the PCIe link, the control register identifying a number count for a plurality of virtual links to be used over the PCIe link, and the control register identifying a priority level for each virtual link;
a plurality of transmit queues in a PCIe root complex, each corresponding to one of the plurality of virtual links established in accordance with the control register, each virtual link having a virtual linkwidth equal to a width of active lanes of the PCIe link uniquely corresponding to a respective virtual link, wherein the PCIe link is configured in Single-Root Input/Output Virtualization (SRIOV);
transmit queue routing circuitry in the PCIe root complex configured to buffer in the transmit queues data packets received from a plurality of virtual machines; and
transmit queue reading circuitry in the PCIe root complex configured to provide data from each of the transmit queues to data transmitting circuitry coupled to a plurality of active lanes of the PCIe link; wherein the transmit queue reading circuitry is configured to provide from one of the transmit queues a number of bytes of data equal to a virtual linkwidth of a respective virtual link corresponding to one of the transmit queues before providing data from another of the transmit queues.
19 . The system of claim 18 , wherein the transmit queue routing circuitry is configured to transfer the data packets from a virtual function associated with a respective virtual machine to the plurality of transmit queues.
20 . The system of claim 19 , wherein each of the virtual functions is configured to include a virtual link identifier in a transaction-layer packet (TLP) header, the virtual link identifier identifying one of the virtual links.
21 . The system of claim 18 , further comprising:
a plurality of receive queues in a PCIe endpoint, each corresponding to one of the virtual links and corresponding to one of the transmit queues; and
receive queue routing logic configured to buffer data received by data receiving circuitry over the plurality of active lanes in the plurality of receive queues, wherein the receive queue routing logic is configured to provide to one of the receive queues a number of bytes of data equal to a virtual linkwidth of a respective virtual link corresponding to one of the receive queues before providing data to another of the receive queues.
22 . The system of claim 18 , wherein at least a first one of the virtual links has a higher virtual linkwidth, and a second one of the virtual links has a lower virtual linkwidth.