Proximity based parity data management
A method includes generating parity data corresponding to a plurality of word lines coupled to blocks of a memory device and generating additional parity data for a block based on a physical location of the block. The method can further include performing a data recovery operation based on the parity data, the additional parity data, or a combination thereof.
1 . An apparatus, comprising:
a memory device comprising a memory structure having a plurality of adjacent blocks coupled to a plurality of word lines; and
a controller coupled to the memory device and configured to:
determine that a block of the plurality of adjacent blocks is an interior block;
generate respective parity data for each of the plurality of adjacent blocks;
generate additional parity data for the interior block; and
perform a data recovery operation based on the parity data, the additional parity data, or a combination thereof.
2 . The apparatus of claim 1 , wherein the controller is configured to generate the additional parity data based on a proximity of the interior block to an edge of a plane in which the block is included.
3 . The apparatus of claim 2 , wherein the controller is configured to generate the additional parity data for the interior block based on a determination that a performance metric of the interior block satisfies a first performance threshold.
4 . The apparatus of claim 2 , wherein the controller is configured to:
designate a block of the plurality of adjacent blocks as an exterior block; and
responsive to determining that a performance metric of the exterior block does not satisfy a second performance threshold, abstaining from generating additional parity data for the exterior block.
5 . The apparatus of claim 1 , wherein the controller is configured to store the additional parity data in the interior block.
6 . The apparatus of claim 1 , wherein the controller is configured to generate the additional parity data based on a performance metric associated with the interior block during an operational lifetime of the memory device.
7 . The apparatus of claim 6 , wherein the performance metric comprises a read window budget (RWB).
8 . The apparatus of claim 7 , wherein the controller is configured to:
determine a RWB value of the interior block;
compare the RWB value to a RWB threshold; and
responsive to determining that the RWB value satisfies the RWB threshold, generate the additional parity data.
9 . The apparatus of claim 8 , wherein the RWB threshold comprises:
a first RWB threshold associated with a first subset of the plurality of adjacent blocks designated as interior blocks; and
a second RWB threshold associated with a second subset of the plurality of adjacent blocks designated as exterior blocks.
10 . The apparatus of claim 1 , wherein the plurality of adjacent blocks are within a same plane of the memory device.
11 . The apparatus of claim 1 , wherein the memory device is a NAND flash memory device.
12 . A method, comprising:
for each word line of a plurality of word lines corresponding to a plurality of adjacent blocks, generating respective parity data corresponding to data stored therein;
wherein a first subset of the plurality of adjacent blocks designated as interior blocks has a first performance threshold associated therewith, and wherein a second subset of the plurality of adjacent blocks designated as exterior blocks has a second performance threshold associated therewith;
responsive to a performance metric of a particular interior block of the first subset satisfying the first performance threshold, generating additional parity data for the particular interior block; and
performing a data recovery operation based on the parity data, the additional parity data, or a combination thereof.
13 . The method of claim 12 , wherein the first performance threshold is less than the second performance threshold.
14 . The method of claim 12 , wherein the first performance threshold comprises a first read window budget (RWB) value, and wherein the second performance threshold comprises a second RWB value.
15 . The method of claim 12 , wherein the first performance threshold is less than a system default performance threshold.
16 . The method of claim 12 , wherein the second performance threshold is greater than a system default performance threshold.
17 . The method of claim 12 , wherein the method further comprises:
generating additional parity data for at least one block included in the first subset responsive to the performance metric of the at least one block included in the first subset satisfying the first performance threshold at a first time; and
generating additional parity data for at least one block included in the second subset responsive to a performance metric of the at least one block in the second subset satisfying the second performance threshold at a second time that is after the first time.
18 . An apparatus, comprising:
a plurality of blocks each coupled to one of a plurality of word lines in a memory device, wherein a quantity of the plurality of blocks is equal to or greater than five blocks per plane in the memory device; and
a controller configured to:
determine that a block of the memory device is an interior block within a memory structure comprised of a plurality of adjacent blocks;
generate parity data for each word line of the plurality of adjacent blocks of the memory device;
wherein a first subset of the plurality of adjacent blocks designated as interior blocks have a first performance threshold associated therewith, and wherein a second subset of the plurality of adjacent blocks designated as exterior blocks have a second performance threshold associated therewith;
responsive to a metric of a particular interior block of the first subset satisfying the first performance threshold, generating additional parity data for the particular interior block of the first subset; and
perform a data recovery operation based on the parity data, the additional parity data, or a combination thereof.
19 . The apparatus of claim 18 , wherein the quantity of the plurality of blocks is equal to six blocks per plane in the memory device, and wherein the controller is configured to designate two innermost blocks relative to an edge of a plane in which the blocks are included as the interior blocks.
20 . The apparatus of claim 18 , wherein the apparatus comprises a solid state drive.