Quantum computing circuit comprising a plurality of chips and method for manufacturing the same
A quantum computing circuit is disclosed herein. An example quantum computing circuit includes a first chip with at least one qubit thereon. The quantum computing circuit also includes a second chip with at least other quantum circuit elements other than qubits thereon. The first chip and the second chip are stacked together in a flip-chip configuration and attached to each other with bump bonding that includes bonding bumps.
1 . A quantum computing circuit comprising:
a first chip including at least one qubit;
a second chip including (i) a quantum circuit refrigerator comprising a superconductor-insulator-normal metal-insulator-superconductor (SINIS) junction and (ii) at least other quantum circuit elements other than qubits; and
a controllable connection between the quantum circuit refrigerator and at least one qubit on the first chip, wherein the controllable connection enables the quantum circuit refrigerator to be controllably used to reset a state of the at least one qubit;
wherein the first chip and the second chip are stacked together in a flip-chip configuration and attached to each other via bump bonding that includes bonding bumps.
2 . The quantum computing circuit according to claim 1 , wherein:
the first chip is made of a first set of constituent materials,
the second chip is made of a second set of constituent materials, and
the first and second sets consist of at least partly different constituent materials.
3 . The quantum computing circuit according to claim 2 , wherein the second set of constituent materials includes at least one material that is not present in the first set of constituent materials and is one of aluminum oxide, copper, palladium, or another non-superconductive metal.
4 . The quantum computing circuit according to claim 1 , wherein:
the first chip is manufactured in a first manufacturing process that includes a first sequence of manufacturing steps,
the second chip is manufactured in a second manufacturing process that includes a second sequence of manufacturing steps, and
the first and second sequences are at least partly different sequences of manufacturing steps.
5 . The quantum computing circuit according to claim 1 , wherein at least some of the bonding bumps are galvanically conductive and constitute galvanically conductive contacts between the first and second chips.
6 . The quantum computing circuit according to claim 1 , wherein one of the first and second chips is a larger chip and the other of the first and second chips is a smaller chip that covers only a part of the larger chip in the flip-chip configuration.
7 . The quantum computing circuit according to claim 6 , wherein:
the larger chip includes at least a first contact pad on a part of its surface facing the smaller chip that is not covered by the smaller chip,
the larger chip includes a first connection connecting the first contact pad and a first galvanically conductive bonding bump, and
the smaller chip includes a second connection connecting the first galvanically conductive bonding bump and a first quantum circuit element on the smaller chip.
8 . The quantum computing circuit according to claim 7 , wherein the first contact pad constitutes a signal connection to the first quantum circuit element.
9 . The quantum computing circuit according to claim 6 , wherein
the smaller chip includes a second contact pad on a surface that faces away from the larger chip, and
the smaller chip includes a third connection through a first conductive via, the third connection connecting the second contact pad to a second quantum circuit element on the surface of the smaller chip facing the larger chip.
10 . The quantum computing circuit according to claim 9 , wherein the larger chip includes a second conductive via connecting a third quantum circuit element on the surface of the larger chip facing the smaller chip that is covered by the smaller chip to a fourth connection that is at least partly located on an opposing surface of the larger chip that faces away from the smaller chip.
11 . The quantum computing circuit according to claim 1 , further comprising a non-galvanic connection for conveying signals between the first and second chips,
wherein the non-galvanic connection includes matching non-galvanic connector structures on surfaces of the first and second chips that face each other.
12 . The quantum computing circuit according to claim 11 , wherein the matching non-galvanic connector structures include mutually aligned conductive areas on the surfaces of the first and second chips facing each other for making a capacitive connection.
13 . The quantum computing circuit according to claim 11 , wherein the matching non-galvanic connector structures include mutually aligned inductive elements for making a magnetic connection.
14 . The quantum computing circuit according to claim 1 , wherein the second chip includes at least one filter that comprises at least one of: a non-superconductive metal, or a lossy dielectric.
15 . The quantum computing circuit according to claim 1 , wherein a separating distance between the first and second chips is between 1 and 100 micrometers.