Non-volatile content addressable memory device having simple cell configuration and operating method of the same
Disclosed are a non-volatile content addressable memory device having a simple cell configuration and/or an operating method thereof. The non-volatile content addressable memory device includes a plurality of unit cells, wherein each of the plurality of unit cells consists of or includes a first ferroelectric transistor and a second ferroelectric transistor The first and second ferroelectric transistors are of different types such as different electrical types from each other. The first and second ferroelectric transistors may be connected in series or in parallel to each other. The first and second ferroelectric transistors may share one word line and one match line. The first and second ferroelectric transistors may share one search line. One of the first and second ferroelectric transistors may be connected to a search line and the other one may be connected to a bar search line. The first and second ferroelectric transistors may share one match line.
1 . A memory device comprising:
a unit cell comprising a first ferroelectric transistor including a first gate layer stacked on a first ferroelectric layer and a second ferroelectric transistor including a second gate layer stacked on a second ferroelectric layer,
wherein one of the first ferroelectric transistor and the second ferroelectric transistor is a P-type transistor and an other of the first ferroelectric transistor and the second ferroelectric transistor is an N-type transistor, and
wherein the unit cell does not include an inverter and a capacitor.
2 . The memory device of claim 1 ,
wherein the first ferroelectric transistor and the second ferroelectric transistor are connected in series to each other or are connected in parallel to each other.
3 . The memory device of claim 1 , wherein the first ferroelectric transistor and the second ferroelectric transistor share one word line and one match line.
4 . The memory device of claim 3 , wherein the first ferroelectric transistor and the second ferroelectric transistor are both between the one word line and the one match line.
5 . The memory device of claim 1 , wherein the first ferroelectric transistor and the second ferroelectric transistor share one search line.
6 . The memory device of claim 3 , wherein one of the first ferroelectric transistor and the second ferroelectric transistor is connected to a search line and an other one of the first ferroelectric transistor and the second ferroelectric transistor is connected to a bar search line.
7 . The memory device of claim 1 , wherein the first ferroelectric transistor and the second ferroelectric transistor share one match line, and the one match line is connected between the first ferroelectric transistor and the second ferroelectric transistor.
8 . The memory device of claim 7 ,
wherein one of the first ferroelectric transistor and the second ferroelectric transistor is connected to a word line.
9 . The memory device of claim 7 ,
wherein the first ferroelectric transistor and the second ferroelectric transistor are connected to one search line.
10 . The memory device of claim 1 ,
wherein the first ferroelectric transistor includes a first source, a first drain, a first channel between the first source and the first drain, and the first gate layer over the first channel,
the second ferroelectric transistor includes a second source, a second drain, a second channel between the second source and the second drain, and the second gate layer over the second channel, and
wherein the first ferroelectric layer is between the first channel and the first gate layer in the first ferroelectric transistor and the second ferroelectric layer is between the second channel and the second gate layer in the second ferroelectric transistor.
11 . The memory device of claim 1 ,
wherein the unit cell does not include another transistor.
12 . The memory device of claim 1 , further comprising a sense amplifier configured to be connected to the unit cell.
13 . The memory device of claim 12 , further comprising a transistor configured to be connected to the unit cell,
wherein the sense amplifier and the transistor are connected to the unit cell via one match line.
14 . The memory device of claim 1 ,
wherein the memory device comprises a static random access memory (SRAM).
15 . The memory device of claim 1 ,
wherein the memory device comprises a content addressable memory.
16 . An operating method of a memory device comprising a unit cell, the operating method comprising:
applying an operating voltage to the unit cell,
wherein the unit cell comprises:
a first ferroelectric transistor including a first gate layer stacked on a first ferroelectric layer; and
a second ferroelectric transistor including a second gate layer stacked on a second ferroelectric layer,
wherein one of the first ferroelectric transistor and the second ferroelectric transistor is a P-type transistor and an other of the first ferroelectric transistor and the second ferroelectric transistor is an N-type transistor, and
wherein the unit cell does not include an inverter and a capacitor.
17 . The operating method of claim 16 ,
wherein the operating voltage is a writing voltage.
18 . The operating method of claim 16 ,
wherein the applying the operating voltage comprises applying an voltage to the unit cell so that at least one of the first ferroelectric transistor and the second ferroelectric transistor becomes an OFF state.
19 . The operating method of claim 18 ,
wherein the operating voltage is a search voltage.
20 . The operating method of claim 19 , further comprising:
measuring a match voltage via a match line connected to the first ferroelectric transistor and the second ferroelectric transistor; and
comparing the match voltage to a reference voltage.