IP Library › Granted Patent US 12,731,732
Granted Patent B2
US 12,731,732 · App. 18/754,232 · Granted Sep 8, 2026

Multilayer ceramic capacitor including internal electrode layers including opposing portions and lead-out portions with different widths

Inventors: Hironori Tsutsumi (Nagaokakyo, JP); Mitsuru Ikeda (Nagaokakyo, JP); Akihiro Yoshida (Nagaokakyo, JP); Takayuki Shimakawa (Nagaokakyo, JP)
Assignee: MURATA MANUFACTURING CO., LTD.
H01G4/2325H01G4/0085H01G4/012H01G4/1227H01G4/30
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Quick Facts
Patent No.
US 12,731,732
App. No.
18/754,232
Granted
Sep 8, 2026
Kind
B2
Abstract

A multilayer ceramic capacitor includes an element body portion including internal electrode layers, and first and second external electrodes. In the internal electrode layers, a width of an opposing portion is larger than a width of a lead-out portion, each of the first and second external electrodes includes a Cu layer on the element body portion including first and second layer portions. The first layer portion has a higher Cu content than the second layer portion, the second layer portion has a higher glass content than the first layer portion. The Cu in the first layer portion is continuous to connect lead-out portions adjacent to each other. In a cross section of the second layer portion extending through a central portion in the width direction and parallel to the thickness and length directions, the glass occupies about 25% or more of an area of the second layer portion.

Claims (34)

1 . A multilayer ceramic capacitor comprising:

an element body portion including a first principal surface and a second principal surface opposite to each other in a thickness direction, a first side surface and a second side surface opposite to each other in a width direction, and a first end surface and a second end surface opposite to each other in a length direction, and a plurality of dielectric layers and a plurality of internal electrode layers laminated in the thickness direction;

a first external electrode on the first end surface; and

a second external electrode on the second end surface; wherein

the plurality of internal electrode layers includes a plurality of first internal electrode layers connected to the first external electrode and a plurality of second internal electrode layers connected to the second external electrode;

each of the plurality of first internal electrode layers includes a first opposing portion opposed to an adjacent second internal electrode layer of the plurality of second internal electrode layers in the thickness direction, and a first lead-out portion connecting the first opposing portion and the first external electrode;

each of the plurality of second internal electrode layers includes a second opposing portion opposed to an adjacent first internal electrode layer of the plurality of first internal electrode layers in the thickness direction, and a second lead-out portion connecting the second opposing portion and the second external electrode;

a width of the first opposing portion in the width direction is larger than a width of the first lead-out portion in the width direction;

a width of the second opposing portion in the width direction is larger than a width of the second lead-out portion in the width direction;

each of the first opposing portion, the first lead-out portion, the second opposing portion, and the second lead-out portion includes an end portion in the width direction;

the end portion of each of the first opposing portion, the first lead-out portion, the second opposing portion, and the second lead-out portion includes at least one gap filled with at least one of the plurality of dielectric layers;

a proportion of the at least one of the plurality of dielectric layers that fills the at least one gap of the first lead-out portion is greater than a proportion of the at least one of the plurality of dielectric layers that fills the at least one gap of the first opposing portion;

a proportion of the at least one of the plurality of dielectric layers that fills the at least one gap of the second lead-out portion is greater than a proportion of the at least one of the plurality of dielectric layers that fills the at least one gap of the second opposing portion;

each of the first external electrode and the second external electrode includes a Cu layer on the element body portion, a Ni plating layer on the Cu layer, and a Sn plating layer on the Ni plating layer;

the Cu layer includes a first layer portion connected to a plurality of the first lead-out portions or a plurality of the second lead-out portions and a second layer portion covering the first layer portion;

the first layer portion has a higher Cu content than the second layer portion and extends in the thickness direction;

the second layer portion has a higher content of a glass than the first layer portion;

the second layer portion has a larger surface area than the first layer portion;

the Cu of the first layer portion of the first external electrode is continuous to connect the first lead-out portions adjacent to each other in the thickness direction;

the Cu of the first layer portion of the second external electrode is continuous to connect the second lead-out portions adjacent to each other in the thickness direction; and

in a cross section of the second layer portion extending through a central portion in the width direction and parallel or substantially parallel to the thickness direction and the length direction, the glass occupies about 25% or more of an area of the second layer portion.

2 . The multilayer ceramic capacitor according to claim 1 , wherein Ni is diffused in the first layer portion.

3 . The multilayer ceramic capacitor according to claim 2 , wherein the first layer portion has a higher Ni concentration as the first layer portion is closer to the element body portion.

4 . The multilayer ceramic capacitor according to claim 1 , wherein a thickness of the second layer portion in the length direction is about 75% or more of a thickness of the Cu layer in the length direction.

5 . The multilayer ceramic capacitor according to claim 1 , wherein the element body portion has a rectangular or substantially rectangular parallelepiped shape.

6 . The multilayer ceramic capacitor according to claim 1 , wherein each of the plurality of dielectric layers includes a perovskite compound including Ba and Ti as a primary component.

7 . The multilayer ceramic capacitor according to claim 6 , wherein each of the plurality of dielectric layers includes at least one of Si, Mg, Mn, V, Cr, or rare earth elements as an additive.

8 . The multilayer ceramic capacitor according to claim 1 , wherein each of the plurality of internal electrode layers includes Ni.

9 . The multilayer ceramic capacitor according to claim 1 , wherein each of the plurality of internal electrode layers includes Sn at an interface with a dielectric layer of the plurality of dielectric layers.

10 . The multilayer ceramic capacitor according to claim 1 , wherein the multilayer ceramic capacitor has a dimension in the length direction of greater than or equal to about 0.2 mm and less than or equal to about 4.5 mm, a dimension in the width direction of greater than or equal to about 0.125 mm and less than or equal to about 3.2 mm, and a dimension in the thickness direction of greater than or equal to about 0.125 mm and less than or equal to about 2.5 mm.

11 . The multilayer ceramic capacitor according to claim 1 , wherein a portion of the plurality of internal electrode layers bulges toward one of the first and second principal surfaces.

12 . The multilayer ceramic capacitor according to claim 11 , wherein the portion of the plurality of internal electrode layers includes about 20% or less of a total number of the plurality of internal electrode layers.

13 . The multilayer ceramic capacitor according to claim 1 , wherein a thickness of the first layer portion is about 25% or less of a total thickness of the Cu layer.

14 . The multilayer ceramic capacitor according to claim 1 , wherein a thickness of the first layer portion is about 5% or less of a total thickness of the Cu layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2024
From: TSUTSUMI, HIRONORI; IKEDA, MITSURU; YOSHIDA, AKIHIRO; SHIMAKAWA, TAKAYUKI
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 067839/0536 →
Priority Claims (1)
JP 2023-109256 · Jul 3, 2023 · national
Continuity (1)
Related Publication 20250014818A1 · Jan 9, 2025
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