Power converter control loop gain adaptation
Described embodiments include a circuit having a comparator with first and second comparator inputs and a comparator output. The second comparator input is coupled to a ripple reference voltage terminal. A switch is coupled between the first comparator input and a ground terminal, and has a switch control terminal that is coupled to the comparator output. A capacitor is coupled between the first comparator input and the ground terminal. A first current source is coupled between a supply terminal and the first comparator input, and has a first current control terminal. A second current source is coupled between a current output terminal and the ground terminal, and has a second current control terminal.
1 . A circuit comprising:
a comparator having first and second comparator inputs and a comparator output, wherein the second comparator input is coupled to a variable reference voltage terminal;
a switch coupled between the first comparator input and a ground terminal, and having a switch control terminal coupled to the comparator output, the switch being enabled responsive to the comparator output having a first state and disabled responsive to the comparator output having a second state;
a capacitor coupled between the first comparator input and the ground terminal;
a first current source coupled between a supply terminal and the first comparator input, and having a first current control terminal; and
a second current source coupled between a current output terminal and the ground terminal, and having a second current control terminal, the second current control terminal coupled to the variable reference voltage terminal.
2 . The circuit of claim 1 , further comprising a digital-to-analog converter (DAC) having a DAC input and a DAC output, wherein the DAC input is coupled to a ripple control signal terminal, and the DAC output is coupled to the variable reference voltage terminal.
3 . The circuit of claim 2 , further comprising a control logic circuit having first, second and third control logic inputs and a control logic output, wherein the first control logic input is coupled to a clock source, the second control logic input is coupled to the comparator output, and the control logic output is coupled to the ripple control signal terminal.
4 . The circuit of claim 3 , wherein the DAC input receives a digital ripple control signal from the ripple control signal terminal, and the DAC output provides an analog conversion of the digital ripple control signal.
5 . The circuit of claim 4 , wherein the digital ripple control signal includes six bits.
6 . The circuit of claim 4 , further comprising an amplifier having first and second amplifier inputs and an amplifier output, wherein the first amplifier input is coupled to a power converter feedback terminal, the second amplifier input is coupled to a power converter reference terminal, and the amplifier output is coupled to the first current control terminal.
7 . The circuit of claim 6 , wherein the capacitor is a first capacitor and the circuit is further comprising a resistor and a second capacitor coupled in series between the amplifier output and the ground terminal.
8 . The circuit of claim 6 , wherein the comparator, the switch, the capacitor, and the first and second current sources are part of a timer circuit configurable to set a switching frequency of the comparator output responsive to a first voltage at the power converter feedback terminal, a second voltage at the power converter reference terminal, and a third voltage at the variable reference voltage terminal.
9 . The circuit of claim 8 , wherein the switching frequency of the comparator output sets a switching frequency of a power converter in a first mode, and the control logic circuit is configurable to set the third voltage responsive to a state of the power converter in a second mode prior to transitioning to the first mode.
10 . The circuit of claim 9 , wherein the state includes a magnitude of a current ripple of the power converter.
11 . The circuit of claim 9 , wherein the control logic circuit is configurable to set a peak current of the power converter in the first mode responsive to an output of the second current source.
12 . The circuit of claim 9 , wherein the control logic circuit is configurable to set a switching frequency of the power converter at a constant value in the second mode.
13 . The circuit of claim 9 , wherein the first mode is a pulse frequency modulation (PFM) mode, and the second mode is a pulse width modulation (PWM) mode.
14 . The circuit of claim 6 , further comprising a V2I circuit having inputs coupled to the DAC output and the amplifier output, the V2I circuits having outputs coupled to the third control logic input.
15 . The circuit of claim 14 , further comprising a valley detection circuit and a peak detection circuit coupled between the V2I circuit and the third control logic input.