Hybrid phase interpolator with unified blender and eye-surf circuit
A unified blender/eye-surf circuit has a first signal path operable in a blender mode to blend phases of two phase-shifted clock signals of a first plurality of phase-shifted clock signals in a fixed ratio to generate a first blended clock signal, and operable in an eye-surf test mode to create variable phase offsets as weighted combinations of pairs phase-shifted clock signals of the first plurality of phase-shifted clock signals to generate the first blended clock signal. A second signal path is operable in the blender mode to blend phases of two phase-shifted clock signals of a second plurality of phase-shifted clock signals in a fixed ratio to generate a second blended clock signal, and operable in an eye-surf test mode to create variable phase offsets as weighted combinations of pairs phase-shifted clock signals of the second plurality of phase-shifted clock signals to generate the second blended clock signal.
1 . A circuit comprising:
a first signal path to receive a first plurality of phase-shifted clock signals, the first signal path:
in a blender mode, blending phases of two phase-shifted clock signals of the first plurality of phase-shifted clock signals in a fixed ratio to generate a first blended clock signal; and
in an eye-surf test mode, creating variable phase offsets as weighted combinations of sets of two phase-shifted clock signals of the first plurality of phase-shifted clock signals to generate the first blended clock signal; and
a second signal path to receive a second plurality of phase-shifted clock signals, the second signal path:
in the blender mode, blending phases of two phase-shifted clock signals of the second plurality of phase-shifted clock signals in a fixed ratio to generate a second blended clock signal; and
in the eye-surf test mode, creating variable phase offsets as weighted combinations of sets of two phase-shifted clock signals of the second plurality of phase-shifted clock signals to generate the second blended clock signal.
2 . The circuit of claim 1 , wherein:
in the eye-surf test mode:
the first signal path weights its combinations of the sets of two phase-shifted clock signals based on an eye-surf code; and
the second signal path weights its combinations of the sets of two phase-shifted clock signals based on an inverted version of the eye-surf code.
3 . The circuit of claim 1 , wherein:
in the blender mode, a phase of the second blended clock signal is offset from a phase of the first blended clock signal by 90 degrees.
4 . The circuit of claim 3 , in the blender mode, the 90 degree offset of the phase of the second blended clock signal from the phase of the first blended clock signal is based on an eye-surf code having a mid-phase code value.
5 . The circuit of claim 1 , wherein:
in the eye-surf test mode, the circuit is configured to generate each of a plurality of values of a clock skew between the first blended clock signal and second blended clock signal, the plurality of values spanning a clock skew range of between 225 and 315 degrees.
6 . The circuit of claim 5 , wherein:
the clock skew range is 270 degrees.
7 . The circuit of claim 1 , wherein:
each phase-shifted clock signal of the first plurality of phase-shifted clock signals is received by the first signal path at a differential pair of transistors; and
each phase-shifted clock signal of the second plurality of phase-shifted clock signals is received by the second signal path at a differential pair of transistors.
8 . The circuit of claim 1 , wherein:
the first plurality of phase-shifted clock signals comprises a series of four phase-shifted clock signals, each phase-shifted 45 degrees from adjacent phase-shifted clock signals in the series; and
the second plurality of phase-shifted clock signals comprises a series of four phase-shifted clock signals, each phase-shifted 45 degrees from adjacent phase-shifted clock signals in the series.
9 . The circuit of claim 8 , wherein:
the first plurality of phase-shifted clock signals comprises a −45° signal, 0° signal, 45° signal, and 90° signal; and
the second plurality of phase-shifted clock signals comprises the 45° signal, the 90° signal, a 135° signal, and a 180° signal.
10 . The circuit of claim 1 , wherein:
the second signal path, in the eye-surf test mode, comprises a plurality of multiplexers to select between two sets of control inputs for generating the weighted combinations of the sets of the two phase-shifted clock signals,
such that the first signal path and second signal path can be controlled to cause the first blended clock signal and second blended clock signal to be either both delayed by a delay amount or offset relative to each other by an offset amount.
11 . A receiver circuit, comprising:
a phase interpolator for processing a clock signal to generate a first plurality of phase-shifted clock signals and a second plurality of phase-shifted clock signals; and
a unified blender and eye-surf circuit comprising:
a first signal path to receive the first plurality of phase-shifted clock signals, the first signal path:
in a blender mode, blending phases of two phase-shifted clock signals of the first plurality of phase-shifted clock signals in a fixed ratio to generate a first blended clock signal; and
in an eye-surf test mode, creating variable phase offsets as weighted combinations of sets of two phase-shifted clock signals of the first plurality of phase-shifted clock signals to generate the first blended clock signal; and
a second signal path to receive the second plurality of phase-shifted clock signals, the second signal path:
in the blender mode, blending phases of two phase-shifted clock signals of the second plurality of phase-shifted clock signals in a fixed ratio to generate a second blended clock signal; and
in the eye-surf test mode, creating variable phase offsets as weighted combinations of sets of two phase-shifted clock signals of the second plurality of phase-shifted clock signals to generate the second blended clock signal.
12 . The receiver circuit of claim 11 , wherein:
the first plurality of phase-shifted clock signals comprises a −45° signal, 0° signal, 45° signal, and 90° signal;
the second plurality of phase-shifted clock signals comprises the 45° signal, the 90° signal, a 135° signal, and a 180° signal;
in the eye-surf test mode:
the first signal path weights its combinations of the sets of two phase-shifted clock signals based on an eye-surf code;
the second signal path weights its combinations of the sets of two phase-shifted clock signals based on an inverted version of the eye-surf code; and
the circuit is configured to generate each of a plurality of values of a clock skew between the first blended clock signal and second blended clock signal, the plurality of values spanning a clock skew range of between 225 and 315 degrees; and
in the blender mode:
a phase of the second blended clock signal is offset from a phase of the first blended clock signal by 90 degrees, based on the eye-surf code having a mid-phase code value.
13 . A method comprising:
operating a first signal path of a receiver in a blender mode to blend phases of two phase-shifted clock signals of a first plurality of phase-shifted clock signals in a fixed ratio to generate a first blended clock signal;
operating a second signal path of the receiver in the blender mode to blend phases of two phase-shifted clock signals of a second plurality of phase-shifted clock signals in a fixed ratio to generate a second blended clock signal;
using the first blended clock signal and the second blended clock signal to sample a data signal of the receiver;
operating the first signal path in an eye-surf test mode to create variable phase offsets as weighted combinations of sets of two phase-shifted clock signals of the first plurality of phase-shifted clock signals to generate the first blended clock signal;
operating a second signal path in the eye-surf test mode to create variable phase offsets as weighted combinations of sets of two phase-shifted clock signals of the second plurality of phase-shifted clock signals to generate the second blended clock signal; and
using the first blended clock signal and the second blended clock signal to determine an eye-width margin of the receiver.
14 . The method of claim 13 , wherein:
in the eye-surf test mode:
the first signal path weights its combinations of the sets of two phase-shifted clock signals based on an eye-surf code; and
the second signal path weights its combinations of the sets of two phase-shifted clock signals based on an inverted version of the eye-surf code.
15 . The method of claim 13 , wherein:
in the blender operating mode, a phase of the second blended clock signal is offset from a phase of the first blended clock signal by 90 degrees.
16 . The method of claim 15 , in the blender operating mode, the 90 degree offset of the phase of the second blended clock signal from the phase of the first blended clock signal is based on an eye-surf code having a mid-phase code value.
17 . The method of claim 13 , wherein:
in the eye-surf test mode, the first signal path and second signal path are configured to generate each of a plurality of values of a clock skew between the first blended clock signal and second blended clock signal, the plurality of values spanning a clock skew range of between 225 and 315 degrees.
18 . The method of claim 17 , wherein:
the clock skew range is 270 degrees.
19 . The method of claim 13 , further comprising:
receiving each phase-shifted clock signal of the first plurality of phase-shifted clock signals at a differential pair of transistors of the first signal path; and
receiving each phase-shifted clock signal of the second plurality of phase-shifted clock signals at a differential pair of transistors of the second signal path.
20 . The method of claim 13 , wherein:
the first plurality of phase-shifted clock signals comprises a series of four phase-shifted clock signals, each phase-shifted 45 degrees from adjacent phase-shifted clock signals in the series; and
the second plurality of phase-shifted clock signals comprises a series of four phase-shifted clock signals, each phase-shifted 45 degrees from adjacent phase-shifted clock signals in the series.