Offset reduction for switched capacitor circuitry
A switched capacitor circuit is provided that may include a first capacitor, a second capacitor, one or more switches coupled between the first and second capacitors, and a first output switch coupled between the first capacitor and a first output terminal. The one or more switches can be controlled by a first pulse signal, and the first output switch can be controlled by a second pulse signal different than the first pulse signal. The switched capacitor circuit can further include a second output switch coupled between the second capacitor and a second output terminal different than the first output terminal. The second output switch can also be controlled by the second pulse signal. The second pulse signal can overlap only a portion of the first pulse signal.
1 . A switched capacitor circuit comprising:
a first capacitor;
a second capacitor;
one or more switches coupled between the first and second capacitors; and
a first output switch coupled between the first capacitor and a first output terminal, wherein:
the one or more switches are controlled by a first pulse signal having a first activation period; and
the first output switch is controlled by a second pulse signal having a second activation period shorter than the first activation period.
2 . The switched capacitor circuit of claim 1 , further comprising:
first sampling switches configured to couple the first capacitor to a differential input port.
3 . The switched capacitor circuit of claim 2 , further comprising:
second sampling switches configured to couple the second capacitor to the differential input port.
4 . The switched capacitor circuit of claim 1 , wherein the one or more switches comprises:
a first switch having a first terminal coupled to the first capacitor and having a second terminal; and
a second switch having a first terminal coupled to the second terminal of the first switch and having a second terminal coupled to the second capacitor.
5 . The switched capacitor circuit of claim 1 , further comprising:
a second output switch coupled between the second capacitor and a second output terminal different than the first output terminal, wherein the second output switch is controlled by the second pulse signal.
6 . The switched capacitor circuit of claim 5 , further comprising:
a third capacitor coupled across the first output terminal and the second output terminal.
7 . The switched capacitor circuit of claim 1 , wherein the first capacitor has a first capacitance value, and wherein the second capacitor has a second capacitance value equal to the first capacitance value.
8 . The switched capacitor circuit of claim 1 , wherein the first activation period has a first rising edge and a corresponding first falling edge, and wherein the second activation period has a second rising edge that occurs after the first rising edge and a corresponding second falling edge that occurs before the first falling edge.
9 . A method of operating a switched capacitor circuit, comprising:
storing a voltage on a first capacitor of the switched capacitor circuit;
storing a voltage on a second capacitor of the switched capacitor circuit;
asserting a first control signal to selectively couple the first and second capacitors in series; and
while the first control signal is asserted, asserting a second control signal, different than the first control signal, to selectively couple the first and second capacitors to an output of the switched capacitor circuit.
10 . The method of claim 9 , further comprising:
activating first switches to selectively couple the first capacitor to an input of the switched capacitor circuit; and
after deactivating the first switches, activating second switches to selectively couple the second capacitor to the input of the switched capacitor circuit.
11 . The method of claim 9 , wherein the first control signal has a first pulse width, and wherein the second control signal has a second pulse width that is shorter than the first pulse width.
12 . The method of claim 9 , wherein the first control signal has a first rising edge and a first falling edge, and wherein the second control signal has a second rising edge occurring after the first rising edge and a second falling edge occurring before the first falling edge.
13 . The method of claim 9 , further comprising:
generating at least the first and second control signals based on three different clock signals.
14 . Switched capacitor circuitry comprising:
a plurality of switched capacitor circuits coupled in parallel between an input and an output of the switched capacitor circuitry; and
a load capacitor coupled across the output and shared among the plurality of switched capacitor circuits, wherein at least one switched capacitor circuit in the plurality of switched capacitor circuits comprises:
a first capacitor;
a second capacitor;
one or more first switches configured to selectively couple the first capacitor to the input;
one or more second switches configured to selectively couple the second capacitor to the input;
one or more third switches configured to selectively couple the first and second capacitors in series; and
one or more fourth switches configured to selectively couple the first and second capacitors to the output.
15 . The switched capacitor circuitry of claim 14 , wherein the one or more third switches are controlled by a first pulse signal, and wherein the one or more fourth switches are controlled by a second pulse signal different than the first pulse signal.
16 . The switched capacitor circuitry of claim 14 , further comprising:
one or more logic circuits configured to gate switch control signals for controlling the first, second, third, and fourth switches in the at least one switched capacitor circuit.
17 . The switched capacitor circuitry of claim 14 , wherein at most one of the plurality of switched capacitor circuits is selectively activated at any point in time.
18 . The switched capacitor circuitry of claim 14 , further comprising:
a switch control signal generation circuit configured to output, based on three clock signals, a first switch control signal to the one or more first switches, a second switch control signal to the one or more second switches, a third switch control signal to the one or more third switches, and a fourth switch control signal to the one or more fourth switches.
19 . The switched capacitor circuitry of claim 18 , wherein the switch control signal generation circuit comprises:
a first delay line configured to receive a first of the three clock signals;
a second delay line configured to receive a second of the three clock signals;
a third delay line configured to receive a third of the three clock signals;
a first logic gate having a first input coupled to the first delay line, a second input coupled to the third delay line, and an output on which the first switch control signal is produced;
a second logic gate having a first input coupled to the second delay line, a second input coupled to the first delay line, and an output on which the second switch control signal is produced;
a third logic gate having a first input coupled to the third delay line, a second input coupled to the second delay line, and an output on which the third switch control signal is produced; and
a fourth logic gate having a first input coupled to the third logic gate, a second input coupled to the third delay line, and an output on which the fourth switch control signal is produced.