Systems and methods for streaming extensions for video encoding
This disclosure is directed to systems and methods of streaming extensions for video encoding. The streaming extensions may enable the bitstream syntax for layered video data to be modified to reduce overhead for encoding. The bitstream syntax may be modified to enable variable length luma and chroma components, and enable the alignment between the layers and slice to be bit aligned to enable increased granularity in image encoding, and to minimize overhead between different elements within the layers.
1 . An electronic device comprising:
a network interface configured to receive a stream of image data corresponding to High Efficiency Video Coding, AOMedia Video 1, ProRes, or Versatile Video Coding, wherein the stream of image data comprises one or more streaming extensions that define modification to a bitstream syntax for the stream of image data, wherein the bitstream syntax comprises a tile syntax that defines an image frame of the stream of image data, wherein the tile syntax comprises a tile header and a slice syntax, and wherein the tile header comprises a layer identification, a channel identification, a horizontal size of a frame, a vertical size of the frame, and a quantization index; and
video encoder circuitry configured to bit-align one or more layers based on concatenating bitstream sections of the stream of image data and to encode one or more slices of the bit-aligned one or more layers based on the bitstream syntax.
2 . The electronic device of claim 1 , wherein the bitstream syntax comprises a luma value that corresponds to a first variable-length code and a chroma value that corresponds to a second variable-length code.
3 . The electronic device of claim 2 , wherein the luma value comprises a first bit value and the chroma value comprises a second bit value.
4 . The electronic device of claim 3 , wherein each of the first bit value and the second bit value are within a range of five to sixteen bits.
5 . The electronic device of claim 1 , wherein the video encoder circuitry is configured to encode the one or more slices in a vertical slice order.
6 . The electronic device of claim 1 , wherein the slice syntax comprises a slice header, luma data, and chroma data.
7 . The electronic device of claim 1 , wherein the video encoder circuitry is configured to bit-align the one or more layers based on concatenating the bitstream sections of the stream of image data on a bit boundary.
8 . The electronic device of claim 1 , wherein the one or more layers comprise one or more scanned discrete cosine transform (DCT) coefficients.
9 . The electronic device of claim 8 , wherein the one or more layers comprise a base layer, and wherein the base layer comprises the one or more scanned DCT coefficients.
10 . The electronic device of claim 1 , wherein one or more elements of the bitstream syntax respectively correspond to a fixed-length bit-string, a fixed-length numerical value, a variable-length code, or any combination thereof.
11 . The electronic device of claim 10 , wherein the fixed-length bit-string, the variable-length code, or both are positioned at leftmost bits of the bitstream syntax, and wherein the fixed-length numerical value is positioned at a most-significant bit of the bitstream syntax.
12 . One or more tangible, non-transitory computer-readable media storing instructions that, when executed by processing circuitry, are configured to cause the processing circuitry to:
receive a stream of image data based on High Efficiency Video Coding, AOMedia Video 1, ProRes, or Versatile Video Coding, wherein the stream of image data comprises one or more streaming extensions that define modification to a bitstream syntax;
determine that the stream of image data comprises one or more layers;
bit-align the one or more layers based on concatenating bitstream sections of the stream of image data based on the bitstream syntax, wherein the bitstream syntax comprises a tile syntax that defines an image frame of the stream of image data, wherein the tile syntax comprises a tile header and a slice syntax, and wherein the tile header comprises a layer identification, a channel identification, a horizontal size of a frame, a vertical size of the frame, and a quantization index; and
encode one or more strips of an image frame of the bit-aligned one or more layers.
13 . The one or more tangible, non-transitory computer-readable media of claim 12 , wherein the one or more layers comprise scanned discrete cosine transform (DCT) coefficients coded within the one or more layers.
14 . The one or more tangible, non-transitory computer-readable media of claim 12 , wherein the bitstream syntax comprises a tile syntax that defines the image frame.
15 . A method comprising:
receiving, via processing circuitry, a stream of High Efficiency Video Coding, AOMedia Video 1, ProRes, or Versatile Video Coding image data, wherein the stream comprises one or more layers and one or more streaming extensions that define modification to a bitstream syntax; and
transmitting, via the processing circuitry, the stream to encoder hardware that is operable to bit-align the one or more layers based on concatenating bitstream sections of the stream and encode one or more slices of the stream based on the bitstream syntax, wherein the bitstream syntax comprises a tile syntax that defines an image frame of the stream of image data, wherein the tile syntax comprises a tile header and a slice syntax, and wherein the tile header comprises a layer identification, a channel identification, a horizontal size of a frame, a vertical size of the frame, and a quantization index.
16 . The method of claim 15 , wherein the bitstream syntax comprises a variable length luma bit size and a variable length chroma bit size.
17 . The method of claim 15 , wherein the bitstream syntax comprises a tile syntax, and wherein the tile syntax comprises a tile header and a slice syntax.
18 . The electronic device of claim 1 , wherein the video encoder circuitry is configured to apply a rate control on the one or more slices of the bit-aligned one or more layers.
19 . The electronic device of claim 18 , wherein the rate control alters the quantization index used for each slice of the one or more slices.
20 . The electronic device of claim 6 , wherein the slice header comprises a first DC coefficient and one or more DC coefficient syntax elements.