IP Library Granted Patent US 12,732,867
Granted Patent B2
US 12,732,867 · App. 17/704,658 · Granted Sep 8, 2026

Edge computing over disaggregated radio access network functions

Inventors: Akhilesh Thyagaturu (Tempe, AZ); Mohit Garg (Hisar, IN); Vinodh Gopal (Westborough, MA); Ned M. Smith (Beaverton, OR)
Assignee: Intel Corporation
H04W28/18H04W28/10
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Quick Facts
Patent No.
US 12,732,867
App. No.
17/704,658
Granted
Sep 8, 2026
Kind
B2
Abstract

The present disclosure describes edge computing over disaggregated radio access network (RAN) infrastructure through dynamic edge data extraction. Edge data is extracted at intermediate stages of RAN processing, provided to edge compute functions, and inserted back into the RAN processing pipeline. These mechanisms allow for the processing of edge data traffic much closer to the data source than existing approaches, which decreases the overall latency and delay. Additionally, these mechanisms do not require changes to already existing network protocols, allowing for non-complex adoption and implementation.

Claims (61)

1 . An apparatus employed as a Radio Access Network (RAN) function in a disaggregated RAN architecture that includes a plurality of RAN functions, the apparatus comprising:

memory circuitry to store program code of the RAN function; and

processor circuitry connected to the memory circuitry, wherein the processor circuitry is to execute the program code to:

receive, from a RAN controller, configuration data including information for routing edge data to an edge compute function,

receive, from a user equipment (UE), a network packet including edge data intended for delivery to an edge computing application (app) based on scheduling information,

extract the edge data from the network packet using data extraction information in the configuration data,

send the extracted edge data to an edge compute function,

obtain processed edge data from the edge compute function,

insert the processed edge data into the network packet, and

send the network packet towards a destination node;

wherein:

the edge compute function is to be configured based upon UE context information of the UE and network address forwarding information.

2 . The apparatus of claim 1 , wherein the memory circuitry is to store an edge-specific dataflow of a network protocol stack, and the processor circuitry is to execute the program code to:

operate edge-specific dataflow to process the extracted edge data for consumption by the edge compute function.

3 . The apparatus of claim 2 , wherein, to insert the processed edge data into the network packet, the processor circuitry is to execute the program code to:

operate edge-specific dataflow to rebuild the network packet to include the processed edge data.

4 . The apparatus of claim 2 , wherein:

the RAN function is configured to perform one or more sublayers of a network protocol stack,

other RAN functions of the plurality of RAN functions are configured to perform other sublayers of the network protocol stack, and

the edge-specific dataflow includes performing operations of the one or more sublayers and performing operations of lightweight versions of the other sublayers of the network protocol stack.

5 . The apparatus of claim 4 , wherein the edge-specific dataflow includes one or more of a set of core network functions, a transport layer protocol, a network layer protocol, and an application layer protocol.

6 . The apparatus of claim 4 , wherein the network protocol stack is a Third Generation Partnership Project (3GPP) Fifth Generation (5G) New Radio (NR) protocol stack including a low physical (PHY) sublayer, a high-PHY sublayer, a Medium Access Control (MAC) sublayer, a Radio Link Control (RLC) sublayer, a Packet Data Convergence Protocol (PDCP) sublayer, a Service Data Protocol (SDAP) sublayer, a Backhaul Adaptation Protocol (BAP) sublayer, and an F1 application protocol (F1AP) sublayer.

7 . The apparatus of claim 6 , wherein the one or more sublayers of the RAN function include the MAC sublayer and the high-PHY sublayer.

8 . The apparatus of claim 6 , wherein:

the scheduling information includes one or more resource blocks (RBs), and the scheduling information includes a slot number in which the network packet is to be carried, a number of orthogonal frequency division multiplexing (OFDM) symbols used to carry the network packet, a cell radio network temporary identifier (C-RNTI), and a modulation and coding scheme (MCS); and

the data extraction information includes a time slot in which the network packet is to be carried, In-phase and Quadrature (I/Q) symbol mapping information, a network address for forwarding data in an uplink (UL) direction, and a network address for data insertion in a downlink (DL) direction.

9 . The apparatus of claim 4 , wherein the network protocol stack is a Institute of Electrical and Electronics Engineers 802 (WiFi) protocol stack including a low-PHY sublayer, a high-PHY, a MAC sublayer, and a logical link control (LLC) sublayer, and the one or more sublayers of the RAN function include the MAC sublayer and the high-PHY sublayer, and wherein the scheduling information includes traffic specification (TSPEC) data or network allocation vector (NAV) setting information.

10 . The apparatus of claim 1 , wherein the processor circuitry is to execute the program code to:

configure the edge compute function with edge compute information and edge data information,

wherein the edge compute information includes user data context information, edge data processing information, and output forwarding information including an ID of an element to which the processed edge data is to be output, and

wherein the edge data information includes the UE context information of the UE, a network address for forwarding data in a UL direction, and a network address for data insertion in a DL direction.

11 . The apparatus of claim 10 , wherein, to extract the edge data from the network packet, the processor circuitry is to execute the program code to: extract the edge data from a data field of the network packet indicated by the data extraction information.

12 . The apparatus of claim 11 , wherein the processor circuitry is to execute the program code, before sending the extracted edge data to the edge compute function, to:

perform one or more preprocessing operations on the extracted edge data, wherein the one or more preprocessing operations on the extracted edge data includes frame ordering operations and cyclic redundancy check (CRC) operations; and

perform one or more processing operations on the extracted edge data, wherein the one or more processing operations on the extracted edge data includes one or more of decoding operations, de-mapping operations, de-encapsulation operations, decryption operations, translation operations, and transformation operations.

13 . The apparatus of claim 12 , wherein the processor circuitry is to execute the program code to:

perform one or more application layer processing operations on the extracted edge data before sending the extracted edge data to the edge compute function and after performing the one or more preprocessing operations and the one or more processing operations,

wherein the one or more application layer processing operations include one or more of provisioning control information elements, flow control, data forwarding handling, performing one or more request methods, resolving a domain name or uniform resource locator (URL), storing data, and accessing data.

14 . The apparatus of claim 13 , wherein the processor circuitry is to execute the program code to:

perform one or more application layer processing operations on the processed edge data obtained from the edge compute function, wherein the one or more application layer processing operations include one or more of provisioning control information elements, flow control, data forwarding handling, performing one or more request methods, resolving a domain name or URL, storing data, accessing data, and formatting the edge data for consumption by a transport layer protocol.

15 . The apparatus of claim 14 , wherein the processor circuitry is to execute the program code, before inserting the extracted edge data into the network packet and after performing the one or more application layer processing operations, to:

perform one or more preprocessing operations on the processed edge data, wherein the one or more preprocessing operations on the processed edge data includes frame ordering operations and CRC operations; and

perform one or more processing operations on the processed edge data, wherein the one or more processing operations on the processed edge data includes one or more of encoding operations, mapping operations, encapsulation operations, encryption operations, translation operations, and transformation operations.

16 . The apparatus of claim 1 , wherein the destination node is the UE, another UE, a RAN node, a RAN function, an edge compute node, a cloud computing service, a web platform, an application server, or a database.

17 . The apparatus of claim 1 , wherein the plurality of RAN functions include one or more remote units (RUs), one or more distributed units (DUs), and one or more centralized units (CUs), wherein the one or more RUs are connected to the one or more DUs via respective next generation fronthaul interface (NGFI)-I links, the one or more DUs are connected to the one or more CUs via respective NGFI-II links, and the one or more CUs are connected to one or more core network functions via respective backhaul links.

18 . A method of operating an edge compute function in association with a Radio Access Network (RAN) function in a disaggregated RAN architecture, the disaggregated RAN architecture including a plurality of RAN functions, the method comprising:

receiving, by the edge compute function from a RAN controller, edge compute information and edge data information based on one or more edge services provided by the edge compute function;

receiving, by the edge compute function, edge data extracted from a network packet by at least one RAN function of the plurality of RAN functions;

processing the extracted edge data by operating the one or more edge apps to provide the one or more edge services involving the extracted edge data; and

providing the processed edge data to a destination node indicated by the edge compute information or the edge data information;

wherein:

the edge compute function is to be configured based upon user equipment (UE) context information of a UE and network address forwarding information.

19 . The method of claim 18 , wherein the method includes:

receiving the edge compute information and the edge data information directly from the RAN controller; or

receiving the edge compute information and the edge data information via the RAN function associated with the edge compute function.

20 . The method of claim 18 , wherein:

the edge compute information includes user data context information, edge data processing information, and output forwarding information including an identifier of an element to which the processed edge data is to be output; and

the edge data information includes the UE context information of the UE, a network address for forwarding data in a UL direction, and a network address for data insertion in a DL direction.

21 . The method of claim 18 , wherein the at least one RAN function is the RAN function associated with the edge compute function or another RAN function not co-located with the edge compute function.

22 . The method of claim 21 , wherein the at least one RAN function implements a Medium Access Control (MAC) scheduler.

23 . The method of claim 18 , wherein the destination node is the at least one RAN function, another RAN function, a UE that generated the edge data, another UE, another edge compute function, a cloud computing service, one or more app servers, or a remote database.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2026
From: INTEL CORPORATION
To: INTEL PRODUCTS IP LLC
Reel/Frame 075991/0096 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2022
From: THYAGATURU, AKHILESH; GOPAL, VINODH; GARG, MOHIT; SMITH, NED M.
To: INTEL CORPORATION
Reel/Frame 059405/0159 →
Continuity (1)
Related Publication 20220232423A1 · Jul 21, 2022
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