Semiconductor device including gate structure
A semiconductor device includes an active region, an isolation region on a side surface of the active region, a gate trench having a first trench portion crossing the active region and a second trench portion in the isolation region, a first gate portion within the first trench portion and a second gate portion within the second trench portion. The first gate portion and the second gate portion each includes a gate dielectric layer, a gate electrode on the gate dielectric layer, partially filling the gate trench, and having an upper surface disposed on a level lower than an upper end of the active region, and an insulative capping pattern on the gate electrode. The first gate portion includes a lower region, an intermediate region on the lower region, and an upper region on the intermediate region. A maximum width of the intermediate region is greater than a maximum width of the lower region and greater than a maximum width of the upper region.
1 . A semiconductor device comprising:
a semiconductor substrate;
an active region on the semiconductor substrate;
an isolation region on the semiconductor substrate, wherein the isolation region is on a side surface of the active region;
a first trench portion crossing the active region;
a second trench portion disposed in the isolation region;
a first gate portion within the first trench portion; and
a second gate portion within the second trench portion,
wherein the first gate portion includes:
a first gate dielectric layer on an inner wall of the first trench portion;
a first gate electrode on the first gate dielectric layer, wherein the first gate electrode partially fills the first trench portion, and has an upper surface at a level lower than an upper surface of the active region; and
a first insulating capping pattern on the first gate electrode,
wherein the second gate portion includes:
a second gate dielectric layer on an inner wall of the second trench portion;
a second gate electrode on the second gate dielectric layer, wherein the second gate electrode partially fills the second trench portion, and has an upper surface at a level lower than an upper surface of the active region; and
a second insulating capping pattern on the second gate electrode,
wherein the first gate portion includes a first lower region, a first intermediate region on the first lower region, and a first upper region on the first intermediate region,
wherein in a first direction, a maximum width of the first intermediate region is greater than a maximum width of the first lower region, and
wherein in the first direction, the maximum width of the first intermediate region is greater than a maximum width of the first upper region.
2 . The semiconductor device of claim 1 , wherein the first gate electrode includes:
a lower region, an intermediate region on the lower region, and an upper region on the intermediate region,
wherein a maximum width of the intermediate region of the first gate electrode is greater than a maximum width of the lower region of the first gate electrode, and
wherein the maximum width of the intermediate region of the first gate electrode is greater than a maximum width of the upper region of the first gate electrode.
3 . The semiconductor device of claim 1 , wherein the second gate electrode includes:
a second lower region;
a second intermediate region on the second lower region, wherein the second intermediate region is at a same level as the first intermediate region; and
a second upper region on the second intermediate region, wherein the second upper region is at the same level as the first upper region, and
wherein the second lower region has a lower end disposed at a level lower than a lower end of the first lower region.
4 . The semiconductor device of claim 3 , wherein in the first direction, a maximum width of the second intermediate region is smaller than the maximum width of the first intermediate region.
5 . The semiconductor device of claim 1 , wherein the first gate electrode includes a first conductive pattern and a second conductive pattern on the first conductive pattern, and
wherein a material of the first conductive pattern is different from a material of the second conductive pattern.
6 . The semiconductor device of claim 5 , wherein the first conductive pattern is positioned to include the maximum width of the first intermediate region.
7 . The semiconductor device of claim 5 , wherein the second conductive pattern is positioned to include the maximum width of the first intermediate region.
8 . The semiconductor device of claim 1 , wherein in the first direction, a width of the first insulating capping pattern of the first gate portion is different from a width of the second insulating capping pattern of the second gate portion.
9 . The semiconductor device of claim 8 , wherein in the first direction, a width of the first insulating capping pattern of the first gate portion is less than a width of the second insulating capping pattern of the second gate portion.
10 . The semiconductor device of claim 1 , wherein in the first direction, a width of the first gate electrode of the first gate portion is different from a width of the second gate electrode of the second gate portion.
11 . The semiconductor device of claim 10 , wherein in the first direction, a width of the first gate electrode of the first gate portion is greater than a width of the second gate electrode of the second gate portion.
12 . The semiconductor device of claim 1 , wherein the first lower region is between a lower end of the first gate portion and a first height,
wherein the first intermediate region is between the first height and a second height,
wherein the first upper region is between the second height and an upper end of the first gate portion,
wherein based on the lower end of the first gate portion, when a height from the lower end to the upper end of the first gate portion is 100, the first height is about 20 and the second height is about 80, and
a portion where the maximum width is located in the first intermediate region is located at a level lower than an upper surface of the first gate electrode.
13 . A semiconductor device comprising:
a semiconductor substrate;
an active region on the semiconductor substrate;
an isolation region on a side surface of the active region and on the semiconductor substrate;
a first trench portion crossing the active region;
a second trench portion in the isolation region;
a first gate portion within the first trench portion; and
a second gate portion within the second trench portion,
wherein the first gate portion includes:
a first gate dielectric layer on an inner wall of the first trench portion;
a first gate electrode on the first gate dielectric layer, wherein the first gate electrode partially fills the first trench portion; and
a first insulating capping pattern on the first gate electrode,
wherein the active region extends in a first direction,
wherein the first gate portion has a first bottom surface curved downwardly, and a first side surface and a second side surface extending from the first bottom surface and opposing each other,
wherein the first side surface includes a first lower portion, and a first upper portion on the first lower portion and having a slope different from a slope of the first lower portion, and
wherein the second side surface includes a second lower portion, and a second upper portion on the second lower portion and having a slope different from a slope of the second lower portion.
14 . The semiconductor device of claim 13 , wherein in the first gate portion, a maximum width of the first gate electrode in the first direction is greater than a maximum width of the first insulating capping pattern in the first direction.
15 . The semiconductor device of claim 13 , wherein the first side surface and the second side surface have an asymmetric structure.
16 . The semiconductor device of claim 13 , wherein one of the second lower portion and the second upper portion has a positive slope and the other has a negative slope.
17 . The semiconductor device of claim 13 , wherein a width of the first insulating capping pattern in the first gate portion is different from a width of a second insulating capping pattern in the second gate portion.
18 . A semiconductor device comprising:
a semiconductor substrate;
an active region on the semiconductor substrate;
an isolation region on a side surface of the active region and on the semiconductor substrate; and
a first gate structure and a second gate structure extending into the isolation region and crossing the active region,
wherein each of the first and second gate structures includes:
a gate electrode and an insulating capping pattern stacked sequentially; and
a gate dielectric layer covering a lower surface of the gate electrode, a side surface of the gate electrode, and a side surface of the insulating capping pattern,
wherein the active region extends in a first direction,
wherein an upper surface of the gate electrode is disposed at a level lower than an upper end of the active region,
wherein each of the first and second gate structures has a first gate portion crossing the active region and a second gate portion extending from the first gate portion and disposed in the isolation region,
wherein a lower end of the second gate portion is disposed at a level lower than a lower end of the first gate portion, and
wherein in the first gate portion, a maximum width of the gate electrode in the first direction is greater than a width of the insulating capping pattern adjacent to the gate electrode in the first direction.
19 . The semiconductor device of claim 18 , wherein in each of the first and second gate structures, the first gate portion has a bottom surface curved downwardly, and a first side surface and a second side surface extending from the bottom surface and opposing each other, and
wherein at least one of the first side surface and the second side surface includes a lower portion and an upper portion having different slopes.
20 . The semiconductor device of claim 18 , wherein the gate electrode includes a first conductive pattern and a second conductive pattern on the first conductive pattern,
wherein a portion of the gate electrode having the maximum width is disposed at a level higher than a middle between an upper surface and a lower surface of the first conductive pattern, and
wherein the portion of the gate electrode having the maximum width is disposed at a level lower than an upper surface of the second conductive pattern.