Three-dimensional nonvolatile memory device including a plurality of memory cells
A three-dimensional nonvolatile memory device includes: a plurality of insulating layers stacked on a substrate in a vertical direction substantially perpendicular to a surface of the substrate; a plurality of channel layers positioned between the plurality of insulating layers, and elongated in a first horizontal direction that is parallel to the surface of the substrate, wherein the plurality of channel layers includes a first metal element; a diffusion stop layer conformally formed in a trench passing through the plurality of insulating layers and the plurality of channel layers in the vertical direction; and a crystalline semiconductor pattern between each of the plurality of channel layers and the diffusion stop layer, wherein the crystalline semiconductor pattern includes a second metal element, wherein a concentration of the second metal element in the crystalline semiconductor pattern is higher than a concentration of the first metal element in the plurality of channel layers.
1 . A three-dimensional nonvolatile memory device comprising:
a plurality of insulating layers stacked on a substrate in a vertical direction substantially perpendicular to a main surface of the substrate;
a plurality of channel layers positioned between the plurality of insulating layers, and elongated in a first horizontal direction that is parallel to the main surface of the substrate, wherein the plurality of channel layers includes a first metal element;
a diffusion stop layer conformally formed in a trench passing through the plurality of insulating layers and the plurality of channel layers in the vertical direction; and
a crystalline semiconductor pattern between each of the plurality of channel layers and the diffusion stop layer, wherein the crystalline semiconductor pattern includes a second metal element,
wherein a concentration of the second metal element in the crystalline semiconductor pattern is higher than a concentration of the first metal element in the plurality of channel layers.
2 . The three-dimensional nonvolatile memory device of claim 1 , wherein the first metal element and the second metal element are identical elements.
3 . The three-dimensional nonvolatile memory device of claim 1 , wherein the first metal element and the second metal element each include one of nickel (Ni) or palladium (Pd).
4 . The three-dimensional nonvolatile memory device of claim 1 , wherein a width of each of the plurality of channel layers in the first horizontal direction is greater than a width of the crystalline semiconductor pattern in the first horizontal direction.
5 . The three-dimensional nonvolatile memory device of claim 1 , wherein the crystalline semiconductor pattern includes:
a first surface in contact with the diffusion stop layer; and
a second surface opposite to the first surface and in contact with each of the plurality of channel layers.
6 . The three-dimensional nonvolatile memory device of claim 1 , wherein the crystalline semiconductor pattern is a single crystal pattern in a (111) crystal direction.
7 . The three-dimensional nonvolatile memory device of claim 1 , further comprising a vertical word line structure passing through at least some of the plurality of channel layers in the vertical direction and connected to the plurality of channel layers.
8 . A three-dimensional nonvolatile memory device comprising:
a first cell array, a second cell array, and a third cell array each including a plurality of insulating layers and a plurality of channel layers alternately stacked on a substrate in a vertical direction substantially perpendicular to a main surface of the substrate, wherein the first to third cell arrays are spaced apart from each other in a first horizontal direction that is parallel to the main surface of the substrate and crosses the vertical direction;
a diffusion stop layer conformally formed in a first trench between the first cell array and the second cell array, wherein the first trench passes through the plurality of insulating layers and the plurality of channel layers in the vertical direction;
a first slit insulating layer filling the first trench, on the diffusion stop layer; and
a first crystalline semiconductor pattern disposed between each of the plurality of channel layers and the diffusion stop layer, wherein the first crystalline semiconductor pattern includes a first metal element,
wherein the plurality of channel layers include the first metal element, wherein the first crystalline semiconductor pattern includes a second metal element, wherein a concentration of the second metal element in the first crystalline semiconductor pattern is higher than a concentration of the first metal element in the plurality of channel layers.
9 . The three-dimensional nonvolatile memory device of claim 8 , wherein a width of the first crystalline semiconductor pattern in a second horizontal direction that crosses the first horizontal direction is greater than a width of the first slit insulating layer in the first horizontal direction.
10 . The three-dimensional nonvolatile memory device of claim 8 , further comprising a second slit insulating layer filling a second trench, between the second cell array and the third cell array, wherein the second trench passes through the plurality of insulating layers and the plurality of channel layers in the vertical direction.
11 . The three-dimensional nonvolatile memory device of claim 10 , further comprising a second crystalline semiconductor pattern disposed between each of the plurality of channel layers and the second slit insulating layer, wherein the second crystalline semiconductor pattern includes a third metal element.
12 . The three-dimensional nonvolatile memory device of claim 11 , wherein the first crystalline semiconductor pattern and the second crystalline semiconductor pattern are each a single crystal pattern in a (111) crystal direction.
13 . The three-dimensional nonvolatile memory device of claim 11 , wherein a concentration of the third metal element in the second crystalline semiconductor pattern is lower than a concentration of the second metal element in the first crystalline semiconductor pattern.
14 . The three-dimensional nonvolatile memory device of claim 11 , wherein a concentration of the third metal element in the second crystalline semiconductor pattern is higher than a concentration of the first metal element in the plurality of channel layers.
15 . The three-dimensional nonvolatile memory device of claim 11 , wherein the first metal element, the second metal element, and the third metal element are identical elements, and each of the first metal element, the second metal element, and the third metal element includes one of nickel (Ni) or palladium (Pd).
16 . The three-dimensional nonvolatile memory device of claim 8 , wherein the first crystalline semiconductor pattern includes:
a first surface in contact with the diffusion stop layer; and
a second surface opposite to the first surface and in contact with each of the plurality of channel layers.
17 . The three-dimensional nonvolatile memory device of claim 8 , wherein a width of each of the plurality of channel layers in the first horizontal direction is greater than a width of the first crystalline semiconductor pattern in the first horizontal direction.
18 . The three-dimensional nonvolatile memory device of claim 8 , wherein the first cell array includes a first bit line pad vertically overlapping the plurality of channel layers,
the second cell array includes a second bit line pad vertically overlapping the plurality of channel layers, and
the diffusion stop layer is disposed between the first bit line pad and the second bit line pad in the first horizontal direction.
19 . A three-dimensional nonvolatile memory device comprising:
a first cell array, a second cell array, and a third cell array each including a plurality of insulating layers and a plurality of channel layers alternately stacked on a substrate in a vertical direction substantially perpendicular to a main surface of the substrate, wherein the first to third cell arrays are spaced apart from each other in a first horizontal direction that is parallel to the main surface of the substrate and crosses the vertical direction;
a vertical word line structure passing through some of the plurality of channel layers in the vertical direction and connected to the plurality of channel layers;
a diffusion stop layer conformally formed in a first trench between the first cell array and the second cell array, wherein the first trench passes through the plurality of insulating layers and the plurality of channel layers in the vertical direction;
a first slit insulating layer filling the first trench, on the diffusion stop layer; and
a first crystalline semiconductor pattern disposed between each of the plurality of channel layers and the diffusion stop layer, wherein the first crystalline semiconductor pattern includes a first metal element,
wherein the plurality of channel layers each include a second metal element,
the first metal element and the second metal element are identical elements, and
a concentration of the first metal element in the first crystalline semiconductor pattern is higher than a concentration of the second metal element in the plurality of channel layers.
20 . The three-dimensional nonvolatile memory device of claim 19 , further comprising:
a second slit insulating layer filling a second trench, between the second cell array and the third cell array, wherein the second trench passes through the plurality of insulating layers and the plurality of channel layers in the vertical direction; and
a second crystalline semiconductor pattern disposed between each of the plurality of channel layers and the second slit insulating layer, wherein the second crystalline semiconductor pattern includes a third metal element,
wherein a concentration of the third metal element in the second crystalline semiconductor pattern is lower than a concentration of the first metal element in the first crystalline semiconductor pattern and higher than a concentration of the second metal element in the plurality of channel layers.