NOR-type memory device, method of manufacturing NOR-type memory device, and electronic apparatus including memory device
View Patent ↗Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device includes: at least one memory cell layer including a first source/drain layer, a first channel layer, a second source/drain layer, a second channel layer, and a third source/drain layer that are stacked on each other; at least one gate stack that extends vertically and includes a gate conductor layer and a memory functional layer between the gate conductor layer and the at least one memory cell layer. A memory cell is defined at an intersection of the gate stack and the memory cell layer. At least one bit line is electrically connected to the second source/drain layer in the memory cell layer; and at least one source line is electrically connected to the first and third source/drain layers in the memory cell layer.
1 . A NOR-type memory device, comprising:
at least one memory cell layer disposed on a substrate, wherein the at least one memory cell layer comprises a first source/drain layer, a first channel layer, a second source/drain layer, a second channel layer, and a third source/drain layer that are sequentially stacked from bottom to top;
at least one gate stack that extends vertically with respect to the substrate to pass through the at least one memory cell layer, wherein the at least one gate stack is surrounded by the at least one memory cell layer, the at least one gate stack comprises a gate conductor layer and a memory functional layer disposed between the gate conductor layer and the at least one memory cell layer, and a memory cell is defined at an intersection of the at least one gate stack and the at least one memory cell layer;
at least one bit line electrically connected to the second source/drain layer in the at least one memory cell layer; and
at least one source line electrically connected to the first source/drain layer and the third source/drain layer in the at least one memory cell layer;
wherein a first cell composition device is defined at an intersection of the at least one gate stack with respect to the first source/drain layer, the first channel layer, and the second source/drain layer in the at least one memory cell layer, a second cell composition device is defined at an intersection of the at least one gate stack with respect to the second source/drain layer, the second channel layer, and the third source/drain layer in the at least one memory cell layer, and the first cell composition device and the second cell composition device are connected in parallel to each other to define a corresponding memory cell.
2 . A NOR-type memory device, comprising:
at least one memory cell layer disposed on a substrate, wherein the at least one memory cell layer comprises a first source/drain layer, a first channel layer, a second source/drain layer, a second channel layer, and a third source/drain layer that are sequentially stacked from bottom to top;
at least one gate stack that extends vertically with respect to the substrate to pass through the at least one memory cell layer, the at least one gate stack is surrounded by the at least one memory cell layer, wherein the at least one gate stack comprises a gate conductor layer and a memory functional layer disposed between the gate conductor layer and the at least one memory cell layer, and a memory cell is defined at an intersection of the at least one gate stack and the at least one memory cell layer;
at least two bit lines respectively electrically connected to the first source/drain layer and the third source/drain layer in the at least one memory cell layer; and
at least one source line electrically connected to the second source/drain layer in the at least one memory cell layer;
wherein a first cell composition device is defined at an intersection of the at least one gate stack with respect to the first source/drain layer, the first channel layer, and the second source/drain layer in the at least one memory cell layer, a second cell composition device is defined at an intersection of the at least one gate stack with respect to the second source/drain layer, the second channel laver, and the third source/drain layer in the at least one memory cell layer, and the first cell composition device and the second cell composition device are connected in parallel to each other to define a corresponding memory cell.
3 . The NOR-type memory device according to claim 1 , wherein the at least one memory cell layer comprises a plurality of memory cell layers, and
wherein the first source/drain layer in each memory cell layer and the third source/drain layer in the memory cell layer below the each memory cell layer are located in the same layer; and/or
wherein the third source/drain layer in each memory cell layer and the first source/drain layer in the memory cell layer above the each memory cell layer are located in the same layer.
4 . The NOR-type memory device according to claim 3 , wherein the first source/drain layer, the first channel layer, the second source/drain layer, the second channel layer, and the third source/drain layer in the at least one memory cell layer are in direct contact with each other, and adjacent memory cell layers are in direct contact with each other.
5 . The NOR-type memory device according to claim 1 , further comprising:
at least one word line; and
at least one select transistor which is disposed on the at least one gate stack respectively and is electrically connected between the at least one word line and the at least one gate stack.
6 . The NOR-type memory device according to claim 5 , wherein the at least one select transistor comprises an active layer self-aligned with an above portion of the at least one gate stack and a select gate stack surrounding a periphery of the active layer.
7 . The NOR-type memory device according to claim 6 , wherein the active layer of the at least one select transistor comprises a bottom portion extending at a top portion of the at least one gate stack and a side portion extending from the bottom portion, and an outer wall of the side portion of the active layer is substantially coplanar to an outer wall of the at least one gate stack.
8 . The NOR-type memory device according to claim 6 , wherein the at least one select transistor comprises a plurality of select transistors, the plurality of select transistors are arranged in a plurality of rows in a first direction, select gate stacks of select transistors in the same row extend continuously with each other in the first direction, and the at least one bit line and the at least one word line extend in a second direction intersecting the first direction.
9 . The NOR-type memory device according to claim 1 , wherein at least one of the first source/drain layer, the first channel layer, the second source/drain layer, the second channel layer, and the third source/drain layer comprises a single crystal semiconductor material.
10 . The NOR-type memory device according to claim 9 , wherein the first channel layer and the second channel layer comprise the single crystal semiconductor material.
11 . The NOR-type memory device according to claim 1 , wherein the memory functional layer comprises at least one of a charge trapping material or a ferroelectric material.
12 . The NOR-type memory device according to claim 1 , wherein at least one of the first source/drain layer, the first channel layer, the second source/drain layer, the second channel layer, and the third source/drain layer surrounds one or more of the at least one gate stack in a transverse direction.
13 . An electronic apparatus comprising the NOR-type memory device according to claim 1 .
14 . The electronic apparatus according to claim 13 , wherein the electronic apparatus comprises a smart phone, a personal computer, a tablet, an artificial intelligence device, a wearable device, a mobile power supply, an automotive electronic device, a communication device, an Internet of Things device, or a headphone.
15 . A method of operating the NOR-type memory device according to claim 1 , comprising:
in one or more access operations of the NOR-type memory device, electrically connecting the at least one bit line as a bit line, and electrically connecting the at least one source line as a source line; and
in further one or more access operations of the NOR-type memory device, electrically connecting the at least one bit line as a source line, and electrically connecting the at least one source line as a bit line.