Three-dimensional ferroelectric semiconductor memory device
A semiconductor memory device is provided. The semiconductor memory device includes: a bit line that extends in a first direction; first and second word lines that extend in a second direction and cross the bit line; an active pattern on the bit line between the first and second word lines, the active pattern including first second vertical parts that are opposite to each other, and a horizontal part that extends between the first and second vertical parts; a first data storage pattern between the first word line and the first vertical part of the active pattern; a second data storage pattern between the second word line and the second vertical part of the active pattern; and a source line connected to the active pattern, the source line extending the first direction and crossing the first word line and the second word line.
1 . A semiconductor memory device, comprising:
a bit line that extends in a first direction;
a first word line that extends in a second direction and crosses the bit line;
a second word line that is spaced apart from the first word line, extends in the second direction and crosses the bit line;
an active pattern on the bit line between the first word line and the second word line, the active pattern comprising a first vertical part and a second vertical part that are opposite to each other, and a horizontal part that extends between the first vertical part and the second vertical part;
a first data storage pattern between the first word line and the first vertical part of the active pattern;
a second data storage pattern between the second word line and the second vertical part of the active pattern; and
a source line connected to the active pattern, the source line extending the first direction and crossing the first word line and the second word line.
2 . The semiconductor memory device of claim 1 , wherein the active pattern comprises an oxide semiconductor.
3 . The semiconductor memory device of claim 1 , wherein the first data storage pattern and the second data storage pattern comprise a ferroelectric material.
4 . The semiconductor memory device of claim 1 , wherein the first data storage pattern and the second data storage pattern extend in the second direction on the bit line.
5 . The semiconductor memory device of claim 1 , wherein, when viewed in vertical section, the first word line and the second word line are between the bit line and the source line.
6 . The semiconductor memory device of claim 1 , wherein the source line is electrically connected to the first vertical part or the second vertical part of the active pattern.
7 . The semiconductor memory device of claim 1 , wherein top surfaces of the first vertical part and a the second vertical part are substantially coplanar with top surfaces of the first data storage pattern and the second data storage pattern.
8 . The semiconductor memory device of claim 1 , wherein top surfaces of the first data storage pattern and the second data storage pattern are substantially coplanar with top surfaces of the first word line and the second word line.
9 . A semiconductor memory device, comprising a plurality of cell array layers that are vertically stacked on a lower dielectric layer, wherein each of the plurality of cell array layers comprises:
a bit line that extends in a first direction;
a first word line that extends in a second direction and crosses the bit line;
a second word line that is spaced apart from the first word line, extends in the second direction and crosses the bit line;
an active pattern on the bit line between the first word line and the second word line, the active pattern comprising a first vertical part and a second vertical part that are opposite to each other, and a horizontal part that extends between the first vertical part and the second vertical part;
a first data storage pattern between the first word line and the first vertical part of the active pattern;
a second data storage pattern between the second word line and the second vertical part of the active pattern; and
a source line that extends in the first direction and crosses the first word line and the second word line.
10 . The semiconductor memory device of claim 1 , wherein the first data storage pattern contacts the bit line.
11 . The semiconductor memory device of claim 10 , wherein the second data storage pattern contacts the bit line.
12 . The semiconductor memory device of claim 1 , wherein a top surface of the first word line and a top surface of the first vertical part are at a same level.
13 . The semiconductor memory device of claim 1 , wherein a top surface of the first word line, a top surface of the first vertical part, a top surface of the second word line and a top surface of the second vertical part are at a same level.
14 . The semiconductor memory device of claim 1 , wherein the first data storage pattern is on a first sidewall of the first word line, and
wherein the semiconductor memory device further comprises a third data storage pattern on a side sidewall of the first word line.
15 . A semiconductor memory device comprising:
a bit line that extends in a first direction;
a first word line and a second word line that extend in a second direction and cross the bit line;
an active pattern on the bit line between the first word line and the second word line, the active pattern comprising a first vertical part and a second vertical part that are opposite to each other, and a horizontal part that extends between the first vertical part and the second vertical part;
a first data storage pattern between the first word line and the first vertical part of the active pattern;
a second data storage pattern between the second word line and the second vertical part of the active pattern;
a source line connected to the active pattern, the source line extending the first direction and crossing the first word line and the second word line; and
lower dielectric patterns that extend in the second direction between a top surface of the bit line and bottom surfaces of the first word line and the second word line.
16 . The semiconductor memory device of claim 1 , further comprising:
a first contact pad coupled to the first vertical part of the active pattern;
a second contact pad coupled to the second vertical part of the active pattern;
a first contact pattern coupled to the first contact pad; and
a second contact pattern coupled to the second contact pad,
wherein, when viewed in plan, the first contact pattern and the second contact pattern are spaced apart from each other across the bit line.
17 . The semiconductor memory device of claim 16 , wherein the source line comprises:
a first source line that extends in the first direction and is connected to the first contact pattern; and
a second source line that extends in the first direction and is connected to the second contact pattern.
18 . The semiconductor memory device of claim 1 , wherein the active pattern further comprises:
a first upper horizontal part on the first word line and connected to the first vertical part; and
a second upper horizontal part on the second word line and connected to the second vertical part.
19 . The semiconductor memory device of claim 18 , further comprising:
a first upper dielectric pattern between the first upper horizontal part of the active pattern and a top surface of the first word line; and
a second upper dielectric pattern between the second upper horizontal part of the active pattern and a top surface of the second word line.