IP Library › Granted Patent US 12,733,282
Granted Patent B2
US 12,733,282 · App. 18/310,194 · Granted Sep 8, 2026

Image sensor

Inventors: Kook Tae Kim (Suwon-si, KR); Jingyun Kim (Suwon-si, KR); Byeongtaek Bae (Suwon-si, KR); Seunghwi Yoo (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10F39/807H10F39/024H10F39/802H10F39/8063H10F39/8067H10F39/811
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Quick Facts
Patent No.
US 12,733,282
App. No.
18/310,194
Granted
Sep 8, 2026
Kind
B2
Abstract

An image sensor may include a substrate having a first surface and a second surface, which are opposite to each other, and micro lenses on the second surface, interconnection lines on the first surface, and a pixel isolation portion in the substrate, the pixel isolation portion configured to isolate pixels from direct contact with each other. The pixel isolation portion may include an insulating isolation pattern and a conductive pattern, wherein the conductive pattern is spaced apart from the substrate, and the insulating isolation pattern is between the substrate and the conductive pattern. The conductive pattern may include a sequential arrangement of a first conductive pattern, a second conductive pattern, and a third conductive pattern on a side surface of the insulating isolation pattern.

Claims (50)

1 . An image sensor, comprising:

a substrate having a first surface and a second surface, the first surface and the second surface being opposite to each other;

micro lenses on the second surface;

interconnection lines on the first surface; and

a pixel isolation portion in the substrate, the pixel isolation portion configured to isolate pixels from direct contact with each other,

wherein the pixel isolation portion includes an insulating isolation pattern and a conductive pattern, the conductive pattern being spaced apart from the substrate, and the insulating isolation pattern being between the substrate and the conductive pattern, and

wherein the conductive pattern includes a sequential arrangement of a first semiconductive pattern, a second semiconductive pattern, and a third semiconductive pattern on a side surface of the insulating isolation pattern, the first semiconductive pattern being in contact with the insulating isolation pattern, and a thickness of the second semiconductive pattern being at least one of larger than a thickness of the first semiconductive pattern or smaller than a thickness of the third semiconductive pattern in a first direction parallel to the first surface.

2 . The image sensor of claim 1 , wherein a grain size of the second semiconductive pattern is larger than a grain size of the first semiconductive pattern.

3 . The image sensor of claim 1 , wherein

the first semiconductive pattern comprises a polycrystalline semiconductor material containing impurities of a first conductivity type, and

the second semiconductive pattern and the third semiconductive patterns comprise a substantially intrinsic polycrystalline semiconductor material.

4 . The image sensor of claim 1 , wherein a grain size of the second semiconductive pattern is about 2 times to about 4 times a grain size of the third semiconductive pattern.

5 . The image sensor of claim 1 , wherein a grain size of the second semiconductive pattern is larger than a grain size of the third semiconductive pattern.

6 . The image sensor of claim 1 , wherein a grain size of the second semiconductive pattern is about 1.5 times to about 6 times a grain size of the first semiconductive pattern.

7 . The image sensor of claim 1 , wherein, the thickness of the second semiconductive pattern is larger than the thickness of the first semiconductive pattern in the first direction.

8 . The image sensor of claim 7 , wherein the thickness of the third semiconductive pattern is larger than the thickness of the second semiconductive pattern in the first direction.

9 . The image sensor of claim 1 , wherein the pixel isolation portion further comprises an insulating gapfill pattern that is between the conductive pattern and the first surface.

10 . The image sensor of claim 9 , wherein a top surface of the insulating gapfill pattern is connected to the second semiconductive pattern and the third semiconductive patterns, the top surface of the insulating gapfill pattern being spaced apart from the first semiconductive pattern.

11 . The image sensor of claim 1 , further comprising a backside insulating layer between the pixel isolation portion and the micro lenses,

wherein a top surface of the third semiconductive pattern is in contact with a bottom surface of the backside insulating layer.

12 . An image sensor, comprising:

a substrate having a first surface and a second surface, the first surface and the second surface being opposite to each other;

micro lenses on the second surface;

interconnection lines on the first surface; and

a pixel isolation portion in the substrate, the pixel isolation portion configured to isolate pixels from direct contact with each other,

wherein the pixel isolation portion includes an insulating isolation pattern and a conductive pattern, the conductive pattern being spaced apart from the substrate, and the insulating isolation pattern being between the substrate and the conductive pattern,

wherein the conductive pattern comprises a sequential arrangement of an outer semiconductive pattern and an inner semiconductive pattern on a side surface of the insulating isolation pattern,

wherein the outer semiconductive pattern includes a polycrystalline semiconductor layer containing impurities of a first conductivity type,

wherein the inner semiconductive pattern includes a substantially intrinsic polycrystalline semiconductor layer, and

wherein a grain size of the inner semiconductive pattern is larger than a grain size of the outer semiconductive pattern.

13 . The image sensor of claim 12 , wherein a grain size of the inner semiconductive pattern is larger at a position close to the outer semiconductive pattern than at a position far from the outer semiconductive pattern.

14 . The image sensor of claim 13 , wherein

the outer semiconductive pattern comprises a first semiconductive pattern,

the inner semiconductive pattern comprises a second semiconductive pattern and a third semiconductive pattern, the third semiconductive pattern being spaced apart from the first semiconductive pattern, and the second semiconductive pattern being between the first semiconductive pattern and the third semiconductive pattern, and

a grain size of the second semiconductive pattern is larger than a grain size of the third semiconductive pattern.

15 . The image sensor of claim 14 , wherein the grain size of the second semiconductive pattern is about 2 times to about 4 times the grain size of the third semiconductive pattern.

16 . The image sensor of claim 14 , wherein a grain size of the first semiconductive pattern is smaller than the grain size of the second semiconductive pattern.

17 . The image sensor of claim 16 , wherein the grain size of the second semiconductive pattern is about 1.5 times to about 6 times the grain size of the first semiconductive pattern.

18 . The image sensor of claim 14 , wherein, a thickness of the second semiconductive pattern is larger than a thickness of the first semiconductive pattern in a first direction parallel to the first surface.

19 . An image sensor, comprising:

a substrate having a first surface and a second surface, the first surface and the second surface being opposite to each other, and the substrate including a clockwise arrangement of first to fourth pixels;

a backside insulating layer in contact with the second surface;

a transfer gate on the first surface of the substrate, in each of the first to fourth pixels;

micro lenses on the second surface;

an interlayer insulating layer covering the first surface of the substrate;

interconnection lines in the interlayer insulating layer; and

a pixel isolation portion in the substrate and between the first to fourth pixels, the pixel isolation portion configured to isolate the first to fourth pixels from direct contact with each other,

wherein the pixel isolation portion includes an insulating isolation pattern and a conductive pattern, the conductive pattern being spaced apart from the substrate, and the insulating isolation pattern being between the substrate and the conductive pattern,

wherein the conductive pattern includes a sequential arrangement of a first semiconductive pattern, a second semiconductive pattern, and a third semiconductive pattern on a side surface of the insulating isolation pattern, and

wherein a grain size of the second semiconductive pattern is larger than a grain size of the third semiconductive pattern.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2023
From: KIM, KOOK TAE; KIM, JINGYUN; BAE, BYEONGTAEK; YOO, SEUNGHWI
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 063568/0257 →
Priority Claims (1)
KR 10-2022-0108618 · Aug 29, 2022 · national
Continuity (1)
Related Publication 20240072089A1 · Feb 29, 2024
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