Configurable leaded package
A semiconductor package includes a base insulating layer; a semiconductor die attached to a portion of the base insulating layer; and a first continuous lead electrically connected to the semiconductor die. The first continuous lead includes a first lateral extension on a first surface of the base insulating layer, a second lateral extension on a second surface of the base insulating layer, and a connecting portion between the first lateral extension and the second lateral extension. The connecting portion penetrates through the base insulating layer.
1 . A semiconductor package comprising:
a base insulating layer;
a semiconductor die attached to a portion of the base insulating layer; and
a first continuous lead electrically connected to the semiconductor die, the first continuous lead including a first lateral extension on a first surface of the base insulating layer, a second lateral extension on a second surface of the base insulating layer, and a connecting portion between the first lateral extension and the second lateral extension; wherein the connecting portion penetrates through the base insulating layer, wherein the first continuous lead includes a uniform construction without any joints between the first lateral extension, the second lateral extension, and the connecting portion.
2 . The semiconductor package of claim 1 further comprising an encapsulation material covering portions of the base insulating layer, the semiconductor die, and the first continuous lead.
3 . The semiconductor package of claim 2 , wherein the second lateral extension does not extend past a periphery of the semiconductor package along a surface of the encapsulation material, from a cross-sectional view of the semiconductor package.
4 . The semiconductor package of claim 2 , wherein a portion of the second lateral extension extends past a periphery of the semiconductor package along a surface the encapsulation material, from a cross-sectional view of the semiconductor package.
5 . The semiconductor package of claim 2 , wherein the encapsulation material includes one of a mold compound, an insulating film, and a sprayed insulative coat.
6 . The semiconductor package of claim 1 , wherein the first lateral extension is substantially parallel to the second lateral extension in at least one view of the semiconductor package.
7 . The semiconductor package of claim 1 , wherein the second lateral extension is exposed to an exterior environment of the semiconductor package.
8 . The semiconductor package of claim 1 , wherein the semiconductor die is directly attached to the base insulating layer via a die attach material.
9 . The semiconductor package of claim 1 , wherein the semiconductor die is electrically connected to the first continuous lead via a bond wire.
10 . The semiconductor package of claim 1 , wherein the semiconductor die is electrically connected to the first continuous lead via a conductive trace.
11 . The semiconductor package of claim 10 , wherein the conductive trace includes an ink residue of a conductive material.
12 . The semiconductor package of claim 1 , wherein the second lateral extension functions as an external lead of the semiconductor package.
13 . The semiconductor package of claim 1 , wherein a thickness of the first lateral extension, the second lateral extension, and the connecting portion are substantially the same from a cross-sectional view of the semiconductor package.
14 . The semiconductor package of claim 1 , wherein the first continuous lead includes copper.
15 . The semiconductor package of claim 1 , wherein the first continuous lead includes a copper base material coated with a conductive material that impacts oxidization of copper.
16 . The semiconductor package of claim 1 , wherein the second lateral extension is attachable to a printed circuit board.
17 . The semiconductor package of claim 1 , wherein the base insulating layer includes a material with a flexibility between 40-50 N/cm.
18 . The semiconductor package of claim 1 , wherein the base insulating layer includes one of a kapton tape, a fiber cloth, a fiber board, a glass cloth, a back grind tape, a plastic plate, and a pre-molded blank.
19 . The semiconductor package of claim 1 , wherein a portion of each of the first lateral extension and the second lateral extension that is adjacent to the connecting portion includes a bend from a cross-sectional view of the semiconductor package.
20 . The semiconductor package of claim 1 , wherein the base insulating layer includes an insulating material in its entirety.
21 . The semiconductor package of claim 1 further comprising a second continuous lead opposite the first continuous lead, wherein a first end of the second lateral extension of the first continuous lead and a second end of the second lateral extension of the second continuous lead face each other in at least one view of the semiconductor package.
22 . A semiconductor package comprising:
a base insulating layer;
a lead including a first lateral extension on a first surface of the base insulating layer and a second lateral extension on a second surface of the base insulating layer, a connecting portion between the first lateral extension and the second lateral extension, the connecting portion penetrating through the base insulating layer; and
a semiconductor die attached to a portion of the first lateral extension and electrically connected to the lead, wherein the lead does not include any joints between the first lateral extension, the second lateral extension, and the connecting portion.
23 . The semiconductor package of claim 22 , wherein the semiconductor die is attached to the portion of the first lateral extension via a die attach material.
24 . The semiconductor package of claim 22 , wherein the semiconductor die is electrically connected to the lead via a bond wire.
25 . The semiconductor package of claim 22 , wherein the semiconductor die is electrically connected to the lead via a bump.
26 . The semiconductor package of claim 22 , wherein the base insulating layer includes an insulating material in its entirety.
27 . The semiconductor package of claim 22 , wherein the lead includes copper.
28 . The semiconductor package of claim 22 , wherein the lead includes a copper base material coated with a conductive material that impacts oxidization of copper.
29 . The semiconductor package of claim 22 further comprising an encapsulation material covering portions of the base insulating layer, the semiconductor die, and the lead.
30 . The semiconductor package of claim 22 , wherein the first lateral extension is substantially parallel to the second lateral extension at least in one view of the semiconductor package.
31 . The semiconductor package of claim 22 , wherein the second lateral extension is exposed from the semiconductor package.
32 . The semiconductor package of claim 22 , wherein the semiconductor die is attached to the base insulating layer via a die attach material.
33 . The semiconductor package of claim 22 , wherein the semiconductor die is electrically connected to the lead via a bond wire.
34 . The semiconductor package of claim 22 , wherein the semiconductor die is electrically connected to the lead via a conductive trace.
35 . The semiconductor package of claim 34 , wherein the conductive trace includes an ink residue of a conductive material.
36 . The semiconductor package of claim 22 , wherein the second lateral extension is attachable to a printed circuit board.
37 . The semiconductor package of claim 22 , wherein the second lateral extension functions as an external lead of the semiconductor package.
38 . A semiconductor package comprising:
a base insulating layer;
a semiconductor die attached to a portion of the base insulating layer; and
a first lead electrically connected to the semiconductor die, wherein the first lead includes a first lateral extension on a first surface of the base insulating layer, a second lateral extension on a second surface of the base insulating layer, and a connecting portion between the first lateral extension and the second lateral extension; wherein an end of the second lateral extension includes a recess.
39 . The semiconductor package of claim 38 , wherein the connecting portion penetrates through the base insulating layer.
40 . The semiconductor package of claim 38 , wherein a thickness of the first lead at the end of the second lateral extension is less than a thickness of the first lead across the first lateral extension, the connecting portion and a portion of the second lateral extension.