Interconnect structure and method of forming same
A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.
1 . A method comprising:
bonding a first semiconductor die to a second semiconductor die at an interface with a copper-silicon oxide nitride (Cu—SiON) bond;
forming a first opening and a second opening in a semiconductor substrate of the first die;
lining the first opening and the second opening with a continuous dielectric liner, wherein the dielectric liner comprises a polyamide layer;
after the lining the first opening and the second opening, extending the first opening through the dielectric liner to expose a conductive portion of a first metallization layer of the first semiconductor die, the first metallization layer comprising conductive portions and dielectric portions, the first opening remaining within the first semiconductor die, wherein residual portions of the continuous dielectric liner remains outside of the first metallization layer;
extending the second opening through the dielectric liner to expose a conductive portion of a second metallization layer of the second semiconductor die, the second opening extending through the interface, wherein the extending the first opening and the extending the second opening are performed simultaneously; and
filling the first opening and the second opening with a conductive material, wherein after the filling at least a portion of the dielectric liner remains.
2 . The method of claim 1 , wherein the bonding the first semiconductor die to the second semiconductor die is performed using a wafer-to-wafer bonding process.
3 . The method of claim 1 , wherein the bonding the first semiconductor die to the second semiconductor die is performed using a chip-to-chip bonding process.
4 . The method of claim 1 , wherein the filling the first opening comprises depositing a seed layer.
5 . The method of claim 4 , wherein the seed layer is alloyed with manganese or aluminum.
6 . The method of claim 1 , wherein the first semiconductor die is a sensor die and the second semiconductor die is an application specific integrated circuit.
7 . A method comprising:
etching a first semiconductor substrate of a first semiconductor die to simultaneously form a first opening and a second opening to a same depth, the first semiconductor die being bonded to a second semiconductor die with a copper-silicon oxide nitride (Cu—SiON) bond, the first semiconductor die comprising a first metallization layer with a first thickness, the first metallization layer comprising a dielectric material and a conductive material, the dielectric material extending across the first semiconductor substrate;
partially filling the first opening and the second opening with a liner, the liner continuously extending from the first opening to the second opening, wherein the liner comprises silicon oxynitride, wherein the liner remains outside of the first metallization layer;
partially filling the first opening and the second opening with a mask material; and
using the mask material as a mask within the first opening and the second opening, etching the first semiconductor die to simultaneously extend the first opening a first distance and to extend the second opening a second distance, wherein the first distance is less than the first thickness and wherein the second distance is greater than the first thickness, wherein the mask material remains within the first opening and the second opening during the entirety of the etching the first semiconductor die to extend the first opening and the second opening.
8 . The method of claim 7 , further comprising depositing a barrier layer to line the first opening and the second opening.
9 . The method of claim 8 , wherein the depositing the barrier layer deposits the barrier layer with a constant thickness.
10 . The method of claim 8 , wherein the depositing the barrier layer deposits the barrier layer with a non-uniform thickness.
11 . The method of claim 7 , further comprising depositing a seed layer adjacent to the barrier layer.
12 . The method of claim 11 , wherein the barrier layer comprises aluminum.
13 . A method comprising:
receiving a first semiconductor die bonded to a second semiconductor die in a face to face configuration, the first semiconductor die having a first surface facing away from the second semiconductor die, wherein the first semiconductor die is bonded to the second semiconductor die with a copper-silicon oxide nitride (Cu—SiON) bond;
simultaneously forming a first opening and a second opening in the first semiconductor die;
forming a first conductive material in the first opening and extending from the first surface to a first metallization layer of the first semiconductor die, the first conductive material being separated from a semiconductor substrate of the first semiconductor die by a first portion of a dielectric liner comprising polyamide, all portions of the dielectric liner being on a single top side of the first metallization layer; and
forming a second conductive material in the second opening and extending from the first surface to a second metallization layer of the second semiconductor die, the second conductive material being separated from the semiconductor substrate by a second portion of the dielectric liner, the dielectric liner being continuous between the first portion and the second portion.
14 . The method of claim 13 , wherein the first semiconductor die and the second semiconductor die are part of a stack of dies, the stack of dies further comprising a third semiconductor die.
15 . The method of claim 13 , wherein the first semiconductor die is a sensor die.
16 . The method of claim 15 , wherein the second semiconductor die is an application specific integrated circuit.
17 . The method of claim 13 , wherein the forming the first conductive material comprises:
depositing a seed layer; and
migrating an adhesive material to an interface between the seed layer and a barrier layer.
18 . The method of claim 17 , further comprising depositing the barrier layer to a constant thickness.
19 . The method of claim 17 , further comprising depositing the barrier layer to a non-uniform thickness.
20 . The method of claim 17 , wherein the barrier layer comprises aluminum.