IP Library › Granted Patent US 12,736,747
Granted Patent B2
US 12,736,747 · App. 18/581,687 · Granted Sep 15, 2026

Photonic chips including a structure enabling measurement of the group velocity of light in a photonic component

Inventors: Hanyi Ding (Colchester, VT); Yusheng Bian (Ballston Lake, NY)
Assignee: GlobalFoundries U.S. Inc.
G02B6/12004G02B6/125G02B6/126G02B2006/1215
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Quick Facts
Patent No.
US 12,736,747
App. No.
18/581,687
Granted
Sep 15, 2026
Kind
B2
Abstract

Structures for a photonic chip that enable the measurement of the group velocity of light in a photonic component and methods of forming such structures. The structure comprises a photonic component having an input and an output, a first waveguide core including a first section coupled to the input of the photonic component, and a second waveguide core including a second section coupled to the output of the photonic component. The structure further comprises a first reflector adjacent to the first section of the first waveguide core, and a second reflector adjacent to the second section of the second waveguide core.

Claims (42)

1 . A structure for a photonic chip, the structure comprising:

a semiconductor substrate;

a photonic component having an input and a first output;

a first waveguide core including a first section coupled to the input of the photonic component;

a second waveguide core including a second section coupled to the first output of the photonic component;

a first reflector adjacent to the first section of the first waveguide core; and

a second reflector adjacent to the second section of the second waveguide core,

wherein the first section of the first waveguide core is disposed between the first reflector and the semiconductor substrate, and the second section of the second waveguide core is disposed between the second reflector and the semiconductor substrate.

2 . The structure of claim 1 wherein the photonic component is a polarization splitter-rotator.

3 . The structure of claim 1 wherein the photonic component has a second output, and further comprising:

a third waveguide core including a third section coupled to the second output of the photonic component; and

a third reflector adjacent to the third section of the third waveguide core.

4 . The structure of claim 1 wherein the first reflector comprises a first waveguide core region, and the second reflector comprises a second waveguide core region.

5 . The structure of claim 4 wherein the first waveguide core region overlaps with the first section of the first waveguide core, and the second waveguide core region overlaps with the second section of the second waveguide core.

6 . The structure of claim 4 wherein the first waveguide core and the second waveguide core comprise a first material, and the first waveguide core region and the second waveguide core region comprise a second material that differs from the first material.

7 . The structure of claim 4 wherein the first waveguide core has a first longitudinal axis and a first width transverse to the first longitudinal axis, the first waveguide core region has a first length parallel to the first longitudinal axis, and the first length ranges from less than three times the first width to one-quarter of the first width.

8 . The structure of claim 7 wherein the second waveguide core has a second longitudinal axis and a second width transverse to the second longitudinal axis, the second waveguide core region has a second length parallel to the second longitudinal axis, and the second length ranges from less than three times the second width to one-quarter of the second width.

9 . A structure for a photonic chip, the structure comprising:

a semiconductor substrate;

a photonic component having an input and a first output;

a first waveguide core including a first section coupled to the input of the photonic component;

a second waveguide core including a second section coupled to the first output of the photonic component;

a first reflector adjacent to the first section of the first waveguide core; and

a second reflector adjacent to the second section of the second waveguide core,

wherein the first reflector is disposed between the first section of the first waveguide core and the semiconductor substrate, and the second reflector is disposed between the second section of the second waveguide core and the semiconductor substrate.

10 . The structure of claim 9 wherein the first reflector comprises a first waveguide core region, and the second reflector comprises a second waveguide core region.

11 . The structure of claim 10 wherein the first section of the first waveguide core overlaps with the first waveguide core region, and the second section of the second waveguide core overlaps with the second waveguide core region.

12 . The structure of claim 10 wherein the first waveguide core and the second waveguide core comprise a first material, and the first waveguide core region and the second waveguide core region comprise a second material that differs from the first material.

13 . The structure of claim 10 wherein the first waveguide core has a first longitudinal axis and a first width transverse to the first longitudinal axis, the first waveguide core region has a first length parallel to the first longitudinal axis, and the first length ranges from less than three times the first width to one-quarter of the first width.

14 . The structure of claim 13 wherein the second waveguide core has a second longitudinal axis and a second width transverse to the second longitudinal axis, the second waveguide core region has a second length parallel to the second longitudinal axis, and the second length ranges from less than three times the second width to one-quarter of the second width.

15 . The structure of claim 1 wherein the first reflector is a first slot in the first section of the first waveguide core, and the second reflector is a second slot in the second section of the second waveguide core.

16 . The structure of claim 15 wherein the first section of the first waveguide core has a first width, the second section of the second waveguide core has a second width, the first slot extends fully across the first width of the first section of the first waveguide core, and the second slot extends fully across the second width of the second section of the second waveguide core.

17 . The structure of claim 1 wherein the first section of the first waveguide core has a first width, the second section of the second waveguide core has a second width, the first reflector is a region of the first section having a third width that is greater than the first width of the first section of the first waveguide core, and the second reflector is a region of the second section having a fourth width that is greater than the second width of the second section of the second waveguide core.

18 . The structure of claim 1 wherein the first section of the first waveguide core has a first waveguide core region, a second waveguide core region, and a third waveguide core region connected by the first waveguide core region to the second waveguide core region, the first waveguide core region has a first width, the second waveguide core region and the third waveguide core region have a second width, and the first width is less than the second width.

19 . A method of forming a structure for a photonic chip, the method comprising:

forming a photonic component having an input and an output;

forming a first waveguide core including a first section coupled to the input of the photonic component;

forming a second waveguide core including a second section coupled to the output of the photonic component;

forming a first reflector adjacent to the first section of the first waveguide core; and

forming a second reflector adjacent to the second section of the second waveguide core,

wherein the first section of the first waveguide core is disposed between the first reflector and a semiconductor substrate, and the second section of the second waveguide core is disposed between the second reflector and the semiconductor substrate.

20 . The structure of claim 9 wherein the photonic component is a polarization splitter-rotator.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2024
From: DING, HANYI; BIAN, YUSHENG
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 066498/0247 →
Continuity (1)
Related Publication 20250264659A1 · Aug 21, 2025
References Cited (17)
US 10816725B2 · Bian · 2020 [cited by examiner]
US 20170163000A1 · Evans · 2017 [cited by examiner]
US 20200225401A1 · Yu · 2020 [cited by examiner]
US 20220299707A1 · Chen · 2022 [cited by examiner]
US 20220308297A1 · Polomoff · 2022 [cited by examiner]
C. J. Oton et al., “Silicon photonic waveguide metrology using Mach-Zehnder interferometers,” Optics Express, vol. 24, Issue 6, pp. 6265-6270 (2016), https://doi.org/10.1364/OE.24.006265. [cited by applicant]
Yufei Xing et al., “Accurate extraction of fabricated geometry using optical measurement,” Photonics Research, vol. 6, Issue 11, pp. 1008-1020 (2018) https://doi.org/10.1364/PRJ.6.001008. [cited by applicant]
Todd H. Stievater et al., “Optical and geometric parameter extraction for photonic integrated circuits,” Optics Express, vol. 30, Issue 9, pp. 14453-14460 (2022), https://doi.org/10.1364/OE.451719. [cited by applicant]
Wesley D. Sacher et al., “Tri-layer silicon nitride-on-silicon photonic platform for ultra-low-loss crossings and interlayer transitions.” Optics Express, vol. 25, Issue 25, pp. 30862-30875 (2017) https://opg.optica.org… [cited by applicant]
K. Giewont et al., “300-mm Monolithic Silicon Photonics Foundry Technology,” in IEEE Journal of Selected Topics in Quantum Electronics, vol. 25, No. 5, pp. 1-11, Sep.-Oct. 2019, Art No. 8200611, doi: 10.1109/JSTQE.2019.… [cited by applicant]
Y. Bian et al., “3D Integrated Laser Attach Technology on a 300-mm Monolithic CMOS Silicon Photonics Platform,” in IEEE Journal of Selected Topics in Quantum Electronics, vol. 29, No. 3: Photon. Elec. Co-Inte. and Adv. … [cited by applicant]
B. Peng et al., “A CMOS Compatible Monolithic Fiber Attach Solution with Reliable Performance and Self-alignment,” in Optical Fiber Communication Conference (OFC) 2020, OSA Technical Digest (Optica Publishing Group, 202… [cited by applicant]
Y. Bian et al., “Towards low-loss monolithic silicon and nitride photonic building blocks in state-of-the-art 300mm CMOS foundry,” in Frontiers in Optics / Laser Science, B. Lee, C. Mazzali, K. Corwin, and R. Jason Jone… [cited by applicant]
M. Rakowski et al., “45nm CMOS—Silicon Photonics Monolithic Technology (45CLO) for next-generation, low power and high speed optical interconnects,” in Optical Fiber Communication Conference (OFC) 2020, OSA Technical Di… [cited by applicant]
Y. Bian et al., “Hybrid III-V laser integration on a monolithic silicon photonic platform,” in Optical Fiber Communication Conference (OFC) 2021, P. Dong, J. Kani, C. Xie, R. Casellas, C. Cole, and M. Li, eds., OSA Tech… [cited by applicant]
Y. Bian et al., “Monolithically integrated silicon nitride platform,” in Optical Fiber Communication Conference (OFC) 2021, P. Dong, J. Kani, C. Xie, R. Casellas, C. Cole, and M. Li, eds., OSA Technical Digest (Optica P… [cited by applicant]
Y. Bian et al., “Monolithically integrated self-aligned SiN edge coupler with <0.6/0.8 dB TE/TM insertion loss, <-39 dB back reflection and >520 mW high-power handling capability,” in Optical Fiber Communication Confere… [cited by applicant]