IP Library › Granted Patent US 12,737,078
Granted Patent B2
US 12,737,078 · App. 19/056,082 · Granted Sep 15, 2026

Sensing circuit and sensing method

Inventors: Chia-Hsien Chu (Hsinchu City, TW); Chun-Chi Lai (Hsinchu City, TW); Ching-Sheng Cheng (Hsinchu City, TW)
Assignee: AUO CORPORATION
G06F3/041662G06F3/0443G06F3/0446G06F3/0447
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Quick Facts
Patent No.
US 12,737,078
App. No.
19/056,082
Granted
Sep 15, 2026
Kind
B2
Abstract

The sensing circuit comprises a plurality of first transceiver capacitors and a plurality of second transceiver capacitors. The plurality of first transceiver capacitors are configured to send and receive a plurality of first detection signals. The plurality of second transceiver capacitors, configured to send and receive a plurality of second detection signals. During a self-capacitance mode, the plurality of first transceiver capacitors are configured to output the plurality of first detection signals and receive the plurality of first detection signals, and the plurality of second transceiver capacitors are configured to output the plurality of second detection signals and receive the plurality of second detection signals. During a mutual-capacitance mode, the plurality of first transceiver capacitors are configured to output the plurality of first detection signals, and the plurality of second transceiver capacitors are configured to receive the plurality of first detection signals.

Claims (31)

1 . A sensing circuit, comprising:

a plurality of first transceiver channels, configured to send and receive a plurality of first detection signals, and the plurality of first detection signals are independent of each other; and

a plurality of second transceiver channels, configured to send and receive a plurality of second detection signals, and the plurality of second detection signals are independent of each other, wherein the plurality of first transceiver channels and the plurality of second transceiver channels are alternately arranged to form an array,

wherein during a self-capacitance mode, each of the plurality of first transceiver channels and the plurality of second transceiver channels are configured to output and receive a corresponding one of a plurality of self-capacitance sensing signals,

wherein during a mutual-capacitance mode, the plurality of first transceiver channels are configured to output a plurality of mutual-capacitance sensing signals, and the plurality of second transceiver channels are configured to receive the plurality of mutual-capacitance sensing signals,

wherein the first transceiver channels and the second transceiver channels output and receive the corresponding one of the plurality of self-capacitance sensing signals during the self-capacitance mode and the first transceiver channels and the second transceiver channels respectively output and receive the mutual-capacitance sensing signals in the mutual-capacitance mode, a touch signal is determined as a signal triggered by a finger if both the plurality of self-capacitance sensing signals and the plurality of mutual-capacitance sensing signals are received from the array, and the touch signal is determined as a noise or a deformation-triggered signal representing a change of an air gap between panels if only the plurality of self-capacitance sensing signals are received from the array; and

wherein the touch signal is calibrated or drop frame when the touch signal is determined as the noise signal or the deformation-triggered signal.

2 . The sensing circuit of claim 1 , wherein each of the plurality of first transceiver channels comprises a first channel, wherein each of the plurality of second transceiver channels comprises a second channel.

3 . The sensing circuit of claim 2 , wherein the first channel is coupled to the second channel in a first row of the array.

4 . The sensing circuit of claim 3 , wherein during the self-capacitance mode, the first channel is configured to output a first self-capacitance sensing signal and receive the first self-capacitance sensing signal, and the second channel is configured to output a second self-capacitance sensing signal and receive the second self-capacitance sensing signal.

5 . The sensing circuit of claim 4 , wherein during the mutual-capacitance mode, the first channel is configured to output a first mutual-capacitance sensing signal, and the second channel is configured to receive the first mutual-capacitance sensing signal.

6 . The sensing circuit of claim 4 , wherein each of the plurality of first transceiver channels further comprises a third channel, wherein each of the plurality of second transceiver channels further comprises a fourth channel.

7 . The sensing circuit of claim 6 , wherein the third channel is coupled to the second channel in the first row of the array, wherein the fourth channel is coupled to the third channel in the first row of the array.

8 . The sensing circuit of claim 7 , wherein during the self-capacitance mode, the third channel is configured to output a third self-capacitance sensing signal and receive the third self-capacitance sensing signal, and the fourth channel is configured to output a fourth self-capacitance sensing signal and receive the fourth self-capacitance sensing signal.

9 . The sensing circuit of claim 8 , wherein during the mutual-capacitance mode, the third channel is configured to output a second mutual-capacitance sensing signal, and the fourth channel is configured to receive the second mutual-capacitance sensing signal.

10 . The sensing circuit of claim 9 , wherein during a first self-capacitance operation period of the self-capacitance mode, the first channel is configured to output the first self-capacitance sensing signal and simultaneously receive the first self-capacitance sensing signal, the second channel is configured to output the second self-capacitance sensing signal and simultaneously receive the second self-capacitance sensing signal, the third channel is configured to output the third self-capacitance sensing signal and simultaneously receive the third self-capacitance sensing signal, and the fourth channel is configured to output the fourth self-capacitance sensing signal and simultaneously receive the fourth self-capacitance sensing signal.

11 . The sensing circuit of claim 10 , wherein during a first mutual-capacitance operation period of the mutual-capacitance mode, the first channel is configured to output a first mutual-capacitance sensing signal, the second channel is configured to simultaneously receive the first mutual-capacitance sensing signal, the third channel is configured to simultaneously output the second mutual-capacitance sensing signal, and the fourth channel is configured to simultaneously receive the second mutual-capacitance sensing signal.

12 . The sensing circuit of claim 2 , wherein the first channel is coupled to the second channel in a first row of the array, wherein each of the plurality of first transceiver channels further comprises a third channel, wherein each of the plurality of second transceiver channels further comprises a fourth channel.

13 . The sensing circuit of claim 12 , wherein the fourth channel is coupled to the first channel in a first column of the array.

14 . The sensing circuit of claim 13 , wherein the third channel is coupled to the fourth channel in a second row of the array, and the third channel is coupled to the second channel.

15 . The sensing circuit of claim 14 , wherein during the self-capacitance mode, the third channel is configured to output a third self-capacitance sensing signal and receive the third self-capacitance sensing signal, and the fourth channel is configured to output a fourth self-capacitance sensing signal and receive the fourth self-capacitance sensing signal.

16 . The sensing circuit of claim 15 , wherein during the mutual-capacitance mode, the third channel is configured to output a second mutual-capacitance sensing signal, and the fourth channel is configured to receive the second mutual-capacitance sensing signal.

17 . The sensing circuit of claim 16 , wherein during a first self-capacitance operation period of the self-capacitance mode, the first channel is configured to output a first self-capacitance sensing signal and simultaneously receive the first self-capacitance sensing signal, the second channel is configured to output a second self-capacitance sensing signal and simultaneously receive the second self-capacitance sensing signal, the third channel is configured to output the third self-capacitance sensing signal and simultaneously receive the third self-capacitance sensing signal, and the fourth channel is configured to output the fourth self-capacitance sensing signal and simultaneously receive the fourth self-capacitance sensing signal.

18 . The sensing circuit of claim 17 , wherein during a first mutual-capacitance operation period of the mutual-capacitance mode, the first channel is configured to output a first mutual-capacitance sensing signal, the second channel is configured to simultaneously receive the first mutual-capacitance sensing signal, the third channel is configured to simultaneously output the second mutual-capacitance sensing signal, and the fourth channel is configured to simultaneously receive the second mutual-capacitance sensing signal.

19 . A sensing method, comprising:

sending and receiving a plurality of first detection signals by a plurality of first transceiver channels, and the plurality of first detection signals being independent of each other;

sending and receiving a plurality of second detection signals by a plurality of second transceiver channels, and the plurality of second detection signals being independent of each other, wherein the plurality of first transceiver channels and the plurality of second transceiver channels are alternately arranged to form an array;

during a self-capacitance mode, outputting and receiving a corresponding one of a plurality of self-capacitance sensing signals by each of the plurality of first transceiver channels and the plurality of second transceiver channels;

during a mutual-capacitance mode, outputting a plurality of mutual-capacitance sensing signals by the plurality of first transceiver channels, and receiving the plurality of mutual-capacitance sensing signals by the plurality of second transceiver channels;

outputting and receiving the corresponding one of the plurality of self-capacitance sensing signals by using the first transceiver channels and the second transceiver channels during the self-capacitance mode and the first transceiver channels and the second transceiver channels respectively output and receive the mutual-capacitance sensing signals in the mutual-capacitance mode, determining a touch signal as a signal triggered by a finger if both the plurality of self-capacitance sensing signals and the plurality of mutual-capacitance sensing signals are received from the array, and determining the touch signal as a deformation-triggered signal representing a change of an air gap between panels if only the plurality of self-capacitance sensing signals are received from the array; and

performing a calibrating operation or a drop frame operation on the touch signal when the touch signal is determined as the deformation-triggered signal.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY DATA PREVIOUSLY RECORDED AT REEL: 70245 FRAME: 557. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 5, 2025
From: CHU, CHIA-HSIEN; LAI, CHUN-CHI; CHENG, CHING-SHENG
To: AUO CORPORATION
Reel/Frame 070410/0903 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 18, 2025
From: CHU, CHIA-HSIEN; LAI, CHUN-CHI; CHENG, CHING-SHENG
To: AUO CORPORATION
Reel/Frame 070245/0557 →
Priority Claims (1)
TW 111104706 · Feb 9, 2022 · national
Continuity (2)
Continuation 17938984 · Sep 7, 2022
Related Publication 20250190072A1 · Jun 12, 2025
References Cited (15)
US 9182865B2 · Chae · 2015 [cited by applicant]
US 9569035B1 · Lee · 2017 [cited by applicant]
US 10684731B2 · Wang et al. · 2020 [cited by applicant]
US 20110175834A1 · Han · 2011 [cited by applicant]
US 20170147141A1 · Khazeni · 2017 [cited by applicant]
US 20180088706A1 · Tanemura · 2018 [cited by applicant]
US 20210026484A1 · Kim · 2021 [cited by applicant]
US 20220404932A1 · Gray · 2022 [cited by examiner]
CN 105094490A · 2015 [cited by applicant]
CN 106484191A · 2017 [cited by applicant]
CN 115113768A · 2022 [cited by examiner]
KR 20230020718A · 2023 [cited by applicant]
TW I412983B · 2013 [cited by applicant]
Machine translation of CN115113768 (Year: 2022). [cited by examiner]
Machine translation of TWI1412983B (Year:2011). [cited by applicant]