Granted Patent B2

US 12,737,307 · App. 18/385,319 · Granted Sep 15, 2026

Inventors: Marc Timothy Jones (Longmont, CO); Daniel Lee Helmick (Thornton, CO)

Assignee: Samsung Electronics Co., Ltd.

G06F13/1642G06F13/128G06F13/4022

Abstract

Claims (47)

1 . A storage device comprising:

a non-volatile storage medium;

a first interface for communicating with a computing device based on a first interface protocol;

a second interface for communicating with a processing element over a data communications network based on a second interface protocol different from the first interface protocol, wherein the second interface is for accessing a network of processing elements including the processing element, the processing element including a first memory; and

a processing circuit coupled to the first interface, the second interface, and the non-volatile storage medium, the processing circuit being configured to:

receive a first request from the computing device via the first interface, the first request identifying a first memory address associated with the first memory;

retrieve first data from the non-volatile storage medium based on the first request; and

transmit the first data to the processing element via the second interface for storing the first data in the first memory based on determining that a condition associated with the first memory address indicates that the first memory address is in an address space associated with the processing element.

2 . The storage device of claim 1 , wherein the first interface is configured for communication with the computing device over a data communication bus.

3 . The storage device of claim 1 , wherein the second interface is configured for point-to-point communication with the processing element over the data communications network.

4 . The storage device of claim 3 , wherein the data communications network includes a switch for transmitting the first data to the processing element based on the first memory address.

5 . The storage device of claim 1 , wherein the processing element includes a graphics processing unit (GPU).

6 . The storage device of claim 1 further comprising a second memory, wherein the processing circuit is further configured to:

receive a second request from the computing device via the first interface;

process second data based on the second request for generating processed second data;

store the processed second data in the second memory;

receive a third request from the computing device via the first interface, the third request identifying a second memory address associated with the second memory; and

transmit the processed second data to the processing element via the second interface for storing the processed second data in the first memory based on the second memory address.

7 . A storage device comprising:

a non-volatile storage medium;

a memory;

a first interface for communicating with a computing device, wherein the first interface is associated with a first interface protocol;

a second interface for communicating with a processing element over a data communications network, wherein the second interface is associated with a second interface protocol different from the first interface protocol, wherein the second interface is for accessing a network of processing elements including the processing element; and

a processing circuit coupled to the first interface, the second interface, the non-volatile storage medium, and the memory, the processing circuit being configured to:

receive a first request from the computing device via the first interface, the first request identifying a memory address associated with the memory;

retrieve data from the non-volatile storage medium based on the first request, and store the data in the memory identified by the memory address;

receive a second request from the processing element over the second interface, the second request identifying the memory address storing the data; and

based on the second request, retrieve the data from the memory and transmit the data to the processing element over the data communications network.

8 . The storage device of claim 7 , wherein the memory is exposed to the data communications network via the second interface.

9 . The storage device of claim 7 , wherein the first request is a first read request and the second request is a second read request.

10 . The storage device of claim 7 , wherein the first interface is configured for communication with the computing device over a data communication bus.

11 . The storage device of claim 7 , wherein the second interface is configured for point-to-point communication with the processing element over the data communications network.

12 . The storage device of claim 11 , wherein the data communications network includes a switch for transmitting the data to the processing element based on the memory address.

13 . The storage device of claim 7 , wherein the processing element includes a graphics processing unit (GPU).

14 . The storage device of claim 7 , wherein the processing element is configured to transmit the second request in response to a third request received by the processing element from the computing device, wherein the third request is for performing a computation using the data.

15 . A method comprising:

receiving a first request from a computing device via a first interface of a storage device, the first interface being associated with a first interface protocol, the first request identifying a first memory address associated with a first memory of a processing element;

retrieving first data from a non-volatile storage medium of the storage device based on the first request; and

transmitting the first data to the processing element via a second interface of the storage device, for storing the first data in the first memory based on determining that a condition associated with the first memory address indicates that the first memory address is in an address space associated with the processing element, wherein the second interface is associated with a second interface protocol different from the first interface protocol, wherein the second interface is for accessing a network of processing elements including the processing element.

16 . The method of claim 15 , wherein the first interface communicates with the computing device over a data communication bus.

17 . The method of claim 15 , wherein the second interface engages in point-to-point communication with the processing element over a data communications network.

18 . The method of claim 15 further comprising:

receiving a second request from the computing device via the first interface;

processing second data based on the second request for generating processed second data;

storing the processed second data in a second memory of the storage device;

receiving a third request from the computing device via the first interface, the third request identifying a second memory address associated with the second memory; and

transmitting the processed second data to the processing element via the second interface for storing the processed second data in the first memory based on the second memory address.

Assignments (1)

Continuity (2)

References Cited (18)