IP Library › Granted Patent US 12,737,381
Granted Patent B2
US 12,737,381 · App. 18/113,264 · Granted Sep 15, 2026

Database synchronization based on memory transfer

Inventors: Diego A. Dompe Gamboa (San Jose, CR); Matthew Aaron Blanford (Roseville, CA); Rodolfo José Piedra Camacho (Cartago, CR)
Assignee: Hewlett Packard Enterprise Development LP
G06F16/27G06F3/0611G06F3/064G06F3/067
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,737,381
App. No.
18/113,264
Granted
Sep 15, 2026
Kind
B2
Abstract

A system for memory-transfer-based database synchronization in an appliance is provided. During operation, the system can receive, from a database manager on an active unit, a notification indicating that a first memory block has been updated due to an update to a first entry in a first database of the active unit. The system can identify a second memory block that stores a corresponding second entry in a second database of a standby unit. The first and second memory blocks can be in first and second memory segments, respectively, of respective memory devices of active and standby devices. The first and second memory segments can be outside of the accessible memory range of the respective operating systems. The system can then replace the content of the second memory block with the content of the first memory block using a memory-transfer operation, thereby synchronizing the first and second entries.

Claims (31)

1 . A method comprising:

receiving, by an appliance from a database management application on an active unit of the appliance, a notification indicating that a first memory block has been updated due to an update to a first entry in a first database of the active unit, wherein the first memory block stores the first entry in a first memory segment of a first memory device of the active unit, and wherein the first memory segment is outside of an accessible memory range of a first operating system of the active unit;

identifying, by the appliance, a second memory block that stores a corresponding second entry in a second database of a standby unit of the appliance, wherein the second memory block is in a second memory segment of a second memory device of the standby unit, and wherein the second memory segment is outside of an accessible memory range of a second operating system of the standby unit; and

replacing, by the appliance, content of the second memory block that is in the second memory segment outside of the accessible memory range of the second operating system with content of the first memory block that is in the first memory segment outside of the accessible memory range of the first operating system using a direct memory-transfer operation managed by a direct memory access (DMA) controller of the appliance independent of the first operating system and the second operating system to synchronize the first and second entries, wherein the direct memory-transfer operation further comprises transferring a cyclic redundancy check (CRC) value from a first data structure associated with the first database of the active unit to a second data structure associated with the second database of the standby unit, and wherein the CRC value is computed based on the content of the first memory block.

2 . The method of claim 1 , further comprising presenting, to the DMA controller of the appliance, the first and second memory segments as a unified flat memory space.

3 . The method of claim 2 , wherein the active and standby units are housed in a chassis of the appliance, and wherein the DMA controller comprises a processor of the chassis outside of the active and standby units.

4 . The method of claim 1 , wherein the notification is triggered in response to completion of a transaction that updates the first entry, and wherein the database management application determines that the first memory block is updated by the transaction.

5 . The method of claim 1 , wherein the first and second entries store same state information for the active and secondary units, respectively, and wherein the state information facilitates a failover from the active unit to the standby unit.

6 . The method of claim 1 , wherein each of the first and second databases is an in-memory key-value-store (memkvs).

7 . The method of claim 1 , wherein the direct memory-transfer operation further comprises data replication from the first memory block to the second memory block using DMA.

8 . The method of claim 7 , wherein the active and standby units are coupled via an interconnect fabric within the appliance, and wherein the interconnect fabric supports DMA-based data replication.

9 . The method of claim 8 , wherein the direct memory-transfer operation further comprises storing the content of the first memory block in a buffer of the interconnect fabric.

10 . An apparatus, comprising:

a chassis;

an active unit comprising a first processor and a first memory device, and having a first operating system;

a standby unit facilitating high availability to the active unit, the standby unit comprising a second processor and a second memory device, and having a second operating system; and

a memory controller comprising a direct memory access (DMA) controller, the memory controller to:

receive, from a database management application on the active unit, a notification indicating that a first memory block has been updated due to an update to a first entry in a first database of the active unit, wherein the first memory block stores the first entry in a first memory segment of the first memory device, and wherein the first memory segment is outside of an accessible memory range of the first operating system of the active unit;

identify a second memory block that stores a corresponding second entry in a second database of a standby unit, wherein the second memory block is in a second memory segment of the second memory device, and wherein the second memory segment is outside of an accessible memory range of the second operating system of the standby unit; and

replace content of the second memory block that is in the second memory segment outside of the accessible memory range of the second operating system with content of the first memory block that is in the first memory segment outside of the accessible memory range of the first operating system using a direct memory-transfer operation managed by the DMA controller independent of the first operating system and the second operating system to synchronize the first and second entries, wherein the direct memory-transfer operation further comprises transferring a cyclic redundancy check (CRC) value from a first data structure associated with the first database of the active unit to a second data structure associated with the second database of the standby unit, and wherein the CRC value is computed based on the content of the first memory block.

11 . The apparatus of claim 10 , wherein the DMA controller is configured to determine the first and second memory segments as a unified flat memory space.

12 . The apparatus of claim 11 , wherein the DMA controller comprises a processor of the chassis outside of the active and standby units.

13 . The apparatus of claim 10 , wherein the notification is triggered in response to completion of a transaction that updates the first entry, and wherein the database management application determines that the first memory block is updated by the transaction.

14 . The apparatus of claim 10 , wherein the first and second entries store same state information for the active and secondary units, respectively, and wherein the state information facilitates a failover from the active unit to the standby unit.

15 . The apparatus of claim 10 , wherein each of the first and second databases is an in-memory key-value-store (memkvs).

16 . The apparatus of claim 10 , wherein the direct memory-transfer operation further comprises data replication from the first memory block to the second memory block using DMA via an interconnect fabric of the chassis.

17 . The apparatus of claim 16 , wherein the direct memory-transfer operation further comprises storing the content of the first memory block in a buffer of the interconnect fabric.

18 . A non-transitory computer-readable storage medium storing instructions that when executed by a processor of an appliance cause the processor to perform a method, the method comprising:

receiving, by a memory controller of the appliance from a database management application on an active unit of the appliance, a notification indicating that a first memory block has been updated due to an update to a first entry in a first database of the active unit, wherein the first memory block stores the first entry in a first memory segment of a first memory device of the active unit, and wherein the first memory segment is outside of an accessible memory range of a first operating system of the active unit;

identifying, by the memory controller, a second memory block that stores a corresponding second entry in a second database of a standby unit of the appliance, wherein the second memory block is in a second memory segment of a second memory device of the standby unit, and wherein the second memory segment is outside of an accessible memory range of a second operating system of the standby unit; and

replacing, by the memory controller, content of the second memory block with content of the first memory block using a direct memory-transfer operation to synchronize the first and second entries, wherein the direct memory-transfer operation further comprises transferring a cyclic redundancy check (CRC) value from a first data structure associated with the first database of the active unit to a second data structure associated with the second database of the standby unit, and wherein the CRC value is computed based on the content of the first memory block.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2023
From: DOMPE GAMBOA, DIEGO A.; BLANFORD, MATTHEW AARON; PIEDRA CAMACHO, RODOLFO JOSÉ
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 062907/0972 →
Continuity (1)
Related Publication 20240289349A1 · Aug 29, 2024
References Cited (12)
US 6073140A · Morgan · 2000 [cited by examiner]
US 6721735B1 · Lee · 2004 [cited by examiner]
US 9298935B1 · Kumar · 2016 [cited by examiner]
US 11360918B1 · Wroblewski · 2022 [cited by examiner]
US 20100241770A1 · Tumblin · 2010 [cited by examiner]
US 20170052723A1 · Voigt · 2017 [cited by examiner]
US 20180013579A1 · Fairweather · 2018 [cited by examiner]
US 20180121099A1 · Vaquero Gonzalez · 2018 [cited by examiner]
US 20180314570A1 · Nazari · 2018 [cited by examiner]
US 20210258308A1 · Avetisov · 2021 [cited by examiner]
US 20220179812A1 · Lin · 2022 [cited by examiner]
Li et al., “KV-Direct: High-Performance In-Memory Key-Value Store with Programmable NIC”, ACM, 2017, 16 Pages. [cited by applicant]