IP Library › Granted Patent US 12,737,599
Granted Patent B2
US 12,737,599 · App. 17/584,302 · Granted Sep 15, 2026

Neuromorphic device and unit synapse device forming the same

Inventors: Chul Jun Lee (Pohang-si, KR); Hyun Sang Hwang (Daegu, KR)
Assignee: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION
G06N3/063
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Quick Facts
Patent No.
US 12,737,599
App. No.
17/584,302
Granted
Sep 15, 2026
Kind
B2
Abstract

Disclosed are a neuromorphic device and a unit synapse devices forming the same. The unit synapse device has a learning device and an inference device. The learning device and the inference device may share a via oxide layer and a common electrode, and a learning operation and an inference operation may be performed in one unit synapse device.

Claims (17)

1 . A unit synapse device, comprising:

a cumulative stack portion formed on a substrate; and

a through-hole portion formed through the cumulative stack portion,

wherein the through-hole portion has a via oxide layer in contact with the cumulative stack portion and a common electrode configured to fill an inside of the via oxide layer, and a learning operation or an inference operation is performed,

wherein the cumulative stack portion comprises:

a first functional metal layer formed on the substrate and having oxygen-reactive metal;

a second interlayer dielectric formed on the first functional metal layer; and

a second functional metal layer having ion source metal formed on the second interlayer dielectric,

wherein the first functional metal layer, the via oxide layer, and the common electrode have a configuration of an interface random access memory (I-RAM) and serve as a learning device for performing the learning operation, and

wherein the second functional metal layer, the via oxide layer, and the common electrode have a configuration of a conductive bridge random access memory (CBRAM) and serve as an inference device for performing the inference operation.

2 . The unit synapse device of claim 1 , wherein the first functional metal layer is electrically connected to a first word line, the second functional metal layer is electrically connected to a second word line, and the common electrode is electrically connected to a bit line.

3 . The unit synapse device of claim 2 , wherein

a first weight is stored in the learning device through the first word line, the first weight is output through the bit line, and

a second weight selected among first weights is transferred to the inference device through the bit line.

4 . The unit synapse device of claim 1 , wherein the learning device and the inference device share the via oxide layer and the common electrode.

5 . The unit synapse device of claim 1 , wherein an oxygen ion vacancy is formed inside the via oxide layer by a voltage applied between the first functional metal layer and the common electrode, and an oxide layer is formed on a surface of the first functional metal layer.

6 . The unit synapse device of claim 1 , wherein a conductive filament is formed inside the via oxide layer by a voltage applied between the second functional metal layer and the common electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2022
From: LEE, CHUL JUN; HWANG, HYUN SANG
To: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION
Reel/Frame 058902/0300 →
Priority Claims (1)
KR 10-2021-0062037 · May 13, 2021 · national
Continuity (1)
Related Publication 20220366227A1 · Nov 17, 2022
References Cited (2)
JP 2004273480A · 2004 [cited by examiner]
JP 2021106262A · 2021 [cited by examiner]