Array substrate, driving method and display device
An array substrate, a driving method thereof, and a display device. In the array substrate, rows of sub-pixels include groups of sub-pixels, each group of sub-pixels includes part of the rows of sub-pixels, and charging times of the part of the rows of sub-pixels are overlapped. A charging time of the second part of the plurality of rows of sub-pixels is longer than a charging time of the first part of the plurality of rows of sub-pixels. During a first time period, a same data signal is written into the first part of the plurality of rows of sub-pixels and the second part of the plurality of rows of sub-pixels, and during a second time period, a data signal written into the second part of the plurality of rows of sub-pixels is at least partially the same as the data signal written during the first time period.
1 . An array substrate, comprising a pixel array formed by a plurality of rows and a plurality of columns of sub-pixels, wherein a plurality of gate lines and a plurality of data lines intersect to define the plurality of rows and the plurality of columns of sub-pixels,
each row of sub-pixels among the plurality of rows of sub-pixels is connected with two adjacent gate lines among the plurality of gate lines;
at least one data line among the plurality of data lines is connected with two adjacent columns of sub-pixels among the plurality of columns of sub-pixels;
the plurality of gate lines are configured to turn on the plurality of rows of sub-pixels, and the plurality of data lines are configured to charge the plurality of columns of sub-pixels that are turned on;
the plurality of rows of sub-pixels comprise a plurality of groups of sub-pixels, each group of sub-pixels comprises part of the plurality of rows of sub-pixels, each row of sub-pixels among the part of the plurality of rows of sub-pixels comprises sub-pixels connected with a same gate line, and charging times of the part of the plurality of rows of sub-pixels are overlapped;
the part of the plurality of rows of sub-pixels comprises a first part of the plurality of rows of sub-pixels and a second part of the plurality of rows of sub-pixels, a charging time of the second part of the plurality of rows of sub-pixels is longer than a charging time of the first part of the plurality of rows of sub-pixels,
during a first time period in which the charging times overlap, a same data signal is written into the first part of the plurality of rows of sub-pixels and the second part of the plurality of rows of sub-pixels,
during a second time period in which the charging times do not overlap, a data signal written into the second part of the plurality of rows of sub-pixels is at least partially the same as the data signal written during the first time period, wherein
a same data line is connected with the plurality of groups of sub-pixels, and a plurality of sub-pixels corresponding to a same color and connected with the same data line are connected with odd rows of gate lines or even rows of gate lines,
two gate lines are taken as a gate line group, two rows of sub-pixels respectively connected with the two gate lines in the gate line group form a sub-pixel group, and sub-pixels connected with the same data line in the sub-pixel group correspond to a same color; and
a plurality of groups of gate lines are sequentially turned on, wherein for each group of gate lines, a gate line connected with the first part of the plurality of rows of sub-pixels is turned on earlier than a gate line connected with the second part of the plurality of rows of sub-pixels.
2 . The array substrate according to claim 1 , wherein in the part of the plurality of rows of sub-pixels, a same data line is connected with a plurality of sub-pixels corresponding to a same color.
3 . The array substrate according to claim 1 , wherein the charging time of the first part of the plurality of rows of sub-pixels is a charging time of one row of sub-pixels, the charging time of the second part of the plurality of rows of sub-pixels is a charging time of two rows of sub-pixels, and the first part of the plurality of rows of sub-pixels and the second part of the plurality of rows of sub-pixels start being charged simultaneously.
4 . The array substrate according to claim 1 , wherein sub-pixels in a same column correspond to a same color,
a plurality of sub-pixels corresponding to red are connected with the odd rows of gate lines, a plurality of sub-pixels corresponding to green are connected with the even rows of gate lines, and a plurality of sub-pixels corresponding to blue and connected with the same data line are connected with a plurality of odd rows of gate lines or a plurality of even rows of gate lines; or
a plurality of sub-pixels corresponding to green are connected with the odd rows of gate lines, a plurality of sub-pixels corresponding to blue are connected with the even rows of gate lines, and a plurality of sub-pixels corresponding to red and connected with the same data line are connected with a plurality of odd rows of gate lines or a plurality of even rows of gate lines; or
a plurality of sub-pixels corresponding to red are connected with the odd rows of gate lines, a plurality of sub-pixels corresponding to blue are connected with the even rows of gate lines, and a plurality of sub-pixels corresponding to green and connected with the same data line are connected with a plurality of odd rows of gate lines or a plurality of even rows of gate lines.
5 . The array substrate according to claim 1 , wherein sub-pixels in a same column correspond to a same color, a plurality of sub-pixels corresponding to red and connected with the same data line are connected with a plurality of odd rows of gate lines or a plurality of even rows of gate lines, a plurality of sub-pixels corresponding to green and connected with the same data line are connected with a plurality of odd rows of gate lines or a plurality of even rows of gate lines, and a plurality of sub-pixels corresponding to blue and connected with the same data line are connected with a plurality of odd rows of gate lines or a plurality of even rows of gate lines.
6 . The array substrate according to claim 1 , wherein an image frame comprises a first display period and a second display period, two adjacent odd rows of gate lines are taken as a group, two adjacent even rows of gate lines are taken as a group, and two rows of sub-pixels connected with each group of gate lines are taken as a group of sub-pixels,
for odd rows of gate lines, a plurality of groups of odd rows of gate lines are sequentially turned on during the first display period; and
for even rows of gate lines, a plurality of groups of eve rows of gate lines are sequentially turned on during the second display period,
wherein, in each group of gate lines, a gate line connected with the first part of the plurality of rows of sub-pixels is turned on earlier than a gate line connected with the second part of the plurality of rows of sub-pixels.
7 . The array substrate according to claim 1 , wherein the plurality of gate lines comprise a plurality of first gate line groups, the plurality of groups of sub-pixels comprise a plurality of first sub-pixel groups, each first gate line group comprises two adjacent gate lines, two rows of sub-pixels connected with each first gate line group form the first sub-pixel group, and two sub-pixels connected with a same data line in each first sub-pixel group correspond to a same color.
8 . The array substrate according to claim 7 , wherein the plurality of groups of sub-pixels further comprise a second sub-pixel group, the second sub-pixel group comprises a plurality of sub-pixels connected with a gate line firstly turned on among the plurality of gate lines, and the plurality of the first sub-pixel groups comprise a plurality of rows of sub-pixels other than the plurality of sub-pixels comprised in the second sub-pixel group.
9 . The array substrate according to claim 7 , wherein the plurality of gate lines are sequentially turned on, and in each group of sub-pixels, a gate line connected with the first part of the plurality of rows of sub-pixels is turned on earlier than a gate line connected with the second part of the plurality of rows of sub-pixels.
10 . A driving method, applied to the array substrate according to claim 1 , wherein the method comprises:
turning on a plurality of gate lines connected with each group of sub-pixels; and
charging, during a period when the plurality of gate lines of each group of sub-pixels are turned on, each group of sub-pixels by the plurality of data lines.
11 . The method according to claim 10 , wherein an image frame comprises a first display period and a second display period, two adjacent odd rows of gate lines are taken as a group, two adjacent even rows of gate lines are taken as a group, and two rows of sub-pixels connected with each group of gate lines are taken as a group of sub-pixels;
wherein the turning on the plurality of gate lines connected with each group of sub-pixels comprises:
during the first display period, turning on the odd rows of gate lines sequentially;
during the second display period, turning on the even rows of gate lines sequentially,
wherein, in each group of gate lines, a gate line connected with the first part of the plurality of rows of sub-pixels is turned on earlier than a gate line connected with the second part of the plurality of rows of sub-pixels.
12 . The method according to claim 10 ,
wherein the turning on the plurality of gate lines connected with each group of sub-pixels comprises:
turning on a plurality of groups of gate lines sequentially, wherein, for each group of gate lines, a gate line connected with the first part of the plurality of rows of sub-pixels is turned on earlier than a gate line connected with the second part of the plurality of rows of sub-pixels.
13 . The method according to claim 10 , wherein the plurality of gate lines comprise a plurality of first gate line groups, each group of sub-pixels comprises two adjacent rows of sub-pixels, each first gate line group comprises two adjacent gate lines, the plurality of groups of sub-pixels comprise a plurality of first sub-pixel groups, and two sub-pixels connected with a same data line in each first sub-pixel group correspond to a same color,
wherein the turning on the plurality of gate lines connected with each group of sub-pixels comprises:
turning on each gate line sequentially, wherein a gate line connected with the first part of the plurality of rows of sub-pixels is turned on earlier than a gate line connected with the second part of the plurality of rows of sub-pixels.
14 . The method according to claim 10 , wherein the charging time of the first part of the plurality of rows of sub-pixels is a charging time of one row of sub-pixels, the charging time of the second part of the plurality of rows of sub-pixels is a charging time of two rows of sub-pixels, and the first part of the plurality of rows of sub-pixels and the second part of the plurality of rows of sub-pixels start being charged simultaneously.
15 . A display device, comprising the array substrate according to claim 1 .
16 . The display device according to claim 15 , further comprising a counter substrate, wherein the counter substrate comprises a color filter layer, the color filter layer comprises a plurality of color filters, the plurality of color filters comprise a plurality of blue color filters, a plurality of red color filters and a plurality of green color filters, and the plurality of color filters are in one-to-one correspondence with the plurality of rows and the plurality of columns of sub-pixels.
17 . The display device according to claim 15 , further comprising a circuit board, wherein the circuit board is provided with a timing controller, and the array substrate further comprises a source driver chip,
wherein the timing controller is coupled with the source driver chip and configured to provide display data to the source driver chip; and
the source driver chip is coupled with the plurality of data lines and configured to provide data signals to the plurality of data lines according to the display data.
18 . The display device according to claim 17 , wherein the circuit board further comprises a level conversion unit, and the array substrate further comprises a gate driving circuit,
the level conversion unit is coupled with the timing controller, the gate driving circuit is connected with the level conversion unit and the plurality of gate lines,
the level conversion unit is configured to receive a plurality of first clock signals provided by the timing controller, convert the plurality of first clock signals into a plurality of second clock signals, and provide the plurality of second clock signals to the gate driving circuit, and
the gate driving circuit is configured to provide gate signals to the plurality of gate lines according to the plurality of second clock signals, so as to control the plurality of gate lines to be turned on.