Stack memory devices communicating via packets
A stack memory device includes a command control circuit configured to latch a command and an address in synchronization with a clock signal to generate a latch command and a latch address, decode the latch command and the latch address to generate a decoding command that is transmitted through a first interface, and encode the decoding command to generate a row control signal and a column control signal that are transmitted through a second interface, and a core control circuit configured to, based on the row control signal and the column control signal, control internal operations performed on a core chip.
1 . A stack memory device comprising:
a command control circuit configured to:
latch a command and an address in synchronization with a clock signal to generate a latch command and a latch address,
decode the latch command and the latch address to generate a decoding command that is transmitted through a first interface and to generate data to a parallelization circuit, and
encode the decoding command to generate a row control signal and a column control signal that are transmitted through a second interface; and
a core control circuit configured to, based on the row control signal and the column control signal, control internal operations performed on a core chip,
wherein the parallelization circuit is configured to receive the data serially to generate parallelized internal data.
2 . The stack memory device of claim 1 , wherein the first interface is different from the second interface.
3 . The stack memory device of claim 1 , wherein the command control circuit comprises:
a first command latch configured to latch the command in synchronization with the clock signal and output the latched command as a latch command;
a second command latch configured to latch the address in synchronization with the clock signal and output the latched address as a latch address;
a command decoder configured to decode the latch command and the latch address to generate the decoding command; and
a command encoder configured to encode the decoding command to generate the row control signal and the column control signal.
4 . The stack memory device of claim 1 , wherein the command control circuit is configured to:
decode the latch command and the latch address to generate a data input control signal to perform a write operation on the core chip; and
decode the latch command and the latch address to generate a data output control signal to perform a read operation on the core chip.
5 . The stack memory device of claim 1 , wherein the parallelization circuit is configured to, based on the data received serially and a data strobe signal, when a data input control signal is generated to perform a write operation on the core chip, generate a write data strobe signal and the parallelized internal data to output to the core control circuit.
6 . The stack memory device of claim 5 , wherein the core control circuit is configured to store the parallelized internal data in the core chip, in synchronization with the write data strobe signal, when the write operation on the core chip is performed.
7 . The stack memory device of claim 1 , further comprising a serialization circuit configured to receive internal data, from the core control circuit, in parallel and in synchronization with a read data strobe signal, when a data output control signal is generated to perform a read operation on the core chip, to generate a data strobe signal and serialized data.
8 . The stack memory device of claim 7 , wherein the core control circuit is configured to output the internal data from the core chip, in synchronization with the read data strobe signal, when the read operation on the core chip is performed.
9 . A stack memory device comprising:
a command decoder configured to decode a latch command and a latch address to generate a decoding command that is transmitted through a first interface and to generate data to a parallelization circuit;
a command encoder configured to encode the decoding command to generate a row control signal and a column control signal that are transmitted through a second interface; and
a core control circuit configured to, based on the row control signal and the column control signal, control internal operations performed on a core chip,
wherein the parallelization circuit is configured to receive the data serially to generate parallelized internal data.
10 . The stack memory device of claim 9 , wherein the first interface is different from the second interface.
11 . The stack memory device of claim 9 , wherein the command decoder is configured to:
decode the latch command and the latch address to generate a data input control signal to perform a write operation on the core chip; and
decode the latch command and the latch address to generate a data output control signal to perform a read operation on the core chip.
12 . The stack memory device of claim 11 , wherein the parallelization circuit is configured to, based on the data received serially and a data strobe signal, when a data input control signal is generated to perform a write operation on the core chip, generate a write data strobe signal and the parallelized internal data to output to the core control circuit.
13 . The stack memory device of claim 12 , wherein the core control circuit is configured to store the parallelized internal data in the core chip, in synchronization with the write data strobe signal, when the write operation on the core chip is performed.
14 . The stack memory device of claim 11 , further comprising a serialization circuit configured to receive internal data from the core control circuit, in parallel and in synchronization with read data strobe signal, when a data output control signal is generated to perform a read operation on the core chip, to generate a data strobe signal and serialized data.
15 . The stack memory device of claim 14 , wherein the core control circuit is configured to output the internal data in synchronization with the read data strobe signal when the read operation on the core chip is performed.
16 . A stack memory device comprising:
a command decoder configured to:
decode a latch command and a latch address to generate a decoding command that is transmitted through a first interface and data to a parallelization circuit,
generate a data input control signal to perform a write operation on the core chip, and
generate a data output control signal to perform a read operation on the core chip;
a command encoder configured to encode the decoding command to generate a row control signal and a column control signal that are transmitted through a second interface; and
a core control circuit configured to, based on the data input control signal, the data output control signal, the row control signal, and the column control signal, control internal operations performed on the core chip,
wherein the parallelization circuit is configured to receive the data serially to generate parallelized internal data.
17 . The stack memory device of claim 16 , wherein the parallelization circuit is configured to, based on the data received serially and a data strobe signal, when a data input control signal is generated, generate a write data strobe signal and the parallelized internal data to output to the core control circuit.
18 . The stack memory device of claim 17 , wherein the core control circuit is configured to store the parallelized internal data in the core chip, in synchronization with the write data strobe signal, when the write operation on the core chip is performed.
19 . The stack memory device of claim 16 , further comprising a serialization circuit configured to receive internal data from the core control circuit, in parallel and in synchronization with read data strobe signal, when the data output control signal is generated, to generate a data strobe signal and serialized data.
20 . The stack memory device of claim 19 , wherein the core control circuit is configured to output the internal data from the core chip, in synchronization with the read data strobe signal, when the read operation on the core chip is performed.
21 . A stack memory device comprising:
a base chip; and
a core chip stacked on the base chip and electrically connected to the base chip,
wherein the base chip comprises:
a command control circuit configured to:
latch a command and an address in synchronization with a clock signal to generate a latch command and a latch address,
decode the latch command and the latch address to generate a decoding command that is transmitted through a first interface and to generate data to a parallelization circuit, and
encode the decoding command to generate a row control signal and a column control signal that are transmitted through a second interface; and
a core control circuit configured to, based on the row control signal and the column control signal, control internal operations performed on the core chip,
wherein the parallelization circuit is configured to receive the data serially to generate parallelized internal data.
22 . The stack memory device of claim 21 , wherein the command control circuit is configured to:
decode the latch command and the latch address to generate a data input control signal to perform a write operation on the core chip; and
decode the latch command and the latch address to generate a data output control signal to perform a read operation on the core chip.
23 . The stack memory device of claim 21 , wherein the parallelization circuit is configured to, based on the data received serially and a data strobe signal, when a data input control signal is generated to perform a write operation on the core chip, generate a write data strobe signal and the parallelized internal data to output to the core control circuit,
wherein the core control circuit is configured to store the parallelized internal data in the core chip, in synchronization with the write data strobe signal, when the write operation on the core chip is performed.
24 . The stack memory device of claim 21 , further comprising a serialization circuit configured to receive internal data from the core control circuit, in parallel and in synchronization with the read data strobe signal, when a data output control signal is generated to perform a read operation on the core chip, to generate a data strobe signal and serialized data,
wherein the core control circuit is configured to output the internal data from the core chip, in synchronization with the read data strobe signal, when the read operation on the core chip is performed.