In-memory compute SRAM with integrated toggle/copy operation and reconfigurable logic operations
Embodiments herein relate to circuitry which allows data to be processed and written back within an SRAM device. In a toggle operation, a memory cell is read and the bit at the complementary output node of a sense amplifier is written back to the memory cell. In a copy operation, a memory cell is read and the bit at the primary output node of the sense amplifier is written to another memory cell in the column. In another aspect, logic operations such as AND, OR, majority, AND-OR, OR-AND, and associated inverse operations can be performed within the SRAM device. This can involve writing data to one or more control memory cells in the same column as the data memory cells involved in the logic operation, and setting the respective word lines to be active concurrently.
1 . An apparatus, comprising:
a sense amplifier coupled to a primary bit line and a complementary bit line of first and second data memory cells and a first control memory cell in a common column, wherein first and second data word lines are coupled to the first and second data memory cells, respectively, and a first control word line is coupled to the first control memory cell; and
a control circuit coupled to the sense amplifier, the control circuit to perform a logic operation involving bits in the first and second data memory cells, wherein to perform the logic operation, the control circuit is to concurrently activate the first and second data word lines and the first control word line and to receive a bit comprising a result of the logic operation from the sense amplifier, wherein the result corresponds to a majority value resolved by the sense amplifier for the first, second, and control memory cells.
2 . The apparatus of claim 1 , wherein:
the sense amplifier comprises a primary output node coupled to the primary bit line and a complementary output node coupled to the complementary bit line; and
the control circuit is to receive the bit comprising the result of the logic operation from the primary output node of the sense amplifier.
3 . The apparatus of claim 1 , wherein:
to perform the logic operation, the control circuit is to write a 1 bit to the first control memory cell; and
the logic operation comprises an OR of the bits in the first and second data memory cells.
4 . The apparatus of claim 1 , wherein:
to perform the logic operation, the control circuit is to write a 0 bit to the first control memory cell; and
the logic operation comprises an AND of the bits in the first and second data memory cells.
5 . The apparatus of claim 1 , wherein:
the sense amplifier is coupled to a third data memory cell and a second control memory cell in the common column;
a third data word line is coupled to the third data memory cell;
a second control word line is coupled to the second control memory cell; and
to perform the logic operation, the control circuit is to concurrently activate the first, second and third data word lines, and the first and second control word lines.
6 . The apparatus of claim 5 , wherein:
to perform the logic operation, the control circuit is to write a 1 bit to the first and second control memory cells; and
the logic operation comprises an OR of bits in the first, second and third data memory cells.
7 . The apparatus of claim 5 , wherein:
to perform the logic operation, the control circuit is to write a 1 bit and a 0 bit to the first and second control memory cells, respectively; and
the logic operation comprises a majority operation for bits in the first, second and third data memory cells.
8 . The apparatus of claim 5 , wherein:
to perform the logic operation, the control circuit is to write a 0 bit to the first and second control memory cells; and
the logic operation comprises an AND of bits in the first, second and third data memory cells.
9 . The apparatus of claim 5 , wherein:
the sense amplifier is coupled to a fourth data memory cell and a third control memory cell in the common column;
a fourth data word line is coupled to the fourth data memory cell;
a third control word line is coupled to the third control memory cell; and
to perform the logic operation, the control circuit is to copy a bit from the third data memory cell to the fourth data memory cell, and concurrently activate the first, second, third and fourth data word lines, and the first, second and third control word lines.
10 . The apparatus of claim 9 , wherein:
to perform the logic operation, the control circuit is to write a 1 bit to the first and second control memory cells and a 0 bit to the third control memory cell; and
the logic operation comprises (A AND B) OR C, where A and B are bits in the first and second data memory cells, respectively, and C is the bit in the third and fourth data memory cells.
11 . The apparatus of claim 9 , wherein:
to perform the logic operation, the control circuit is to write a 1 bit to the first control memory cell and a 0 bit to the second and third control memory cells; and
the logic operation comprises (A OR B) AND C, where A and B are bits in the first and second data memory cells, respectively, C is a bit in the third and fourth data memory cells.
12 . An apparatus, comprising:
a memory device to store instructions; and
a processor to execute the instructions to perform a logic operation involving bits in first, second and third data memory cells, wherein:
the first, second and third data memory cells are in a common column with first and second control memory cells;
first, second and third data word lines are coupled to the first, second and third data memory cells, respectively;
first and second control word lines are coupled to the first and second control memory cells, respectively; and
to perform the logic operation, the processor is to write data to the first and second control memory cells based on the logic operation, concurrently activate the first, second and third data word lines and the first and second control word lines, and receive a bit comprising a result of the logic operation from a sense amplifier, wherein the result corresponds to a majority value resolved by the sense amplifier for the first, second, third, first control, and second control memory cells.
13 . The apparatus of claim 12 , wherein:
the common column comprises a primary bit line and a complementary bit line;
the sense amplifier comprises a primary output node coupled to the primary bit line and a complementary output node coupled to the complementary bit line;
to perform the logic operation, the processor is to write a 1 bit to the first and second control memory cells;
the logic operation comprises A OR B OR C, where A, B and C are bits in the first, second and third data memory cells, respectively; and
the bit comprising the result of the logic operation is received from the primary output node of the sense amplifier.
14 . The apparatus of claim 12 , wherein:
the common column comprises a primary bit line and a complementary bit line;
the sense amplifier comprises a primary output node coupled to the primary bit line and a complementary output node coupled to the complementary bit line;
to perform the logic operation, the processor is to write a 1 bit to the first control memory cell and a 0 bit to the second control memory cell;
the logic operation comprises a majority operation for bits in the first, second and third data memory cells; and
the bit comprising the result of the logic operation is received from the primary output node of the sense amplifier.
15 . The apparatus of claim 12 , wherein:
the common column comprises a primary bit line and a complementary bit line;
the sense amplifier comprises a primary output node coupled to the primary bit line and a complementary output node coupled to the complementary bit line;
to perform the logic operation, the processor is to write a 0 bit to the first and second control memory cells;
the logic operation comprises A AND B AND C, where A, B and C are bits in the first, second and third data memory cells; and
the bit comprising the result of the logic operation is received from the primary output node of the sense amplifier.
16 . The apparatus of claim 12 , wherein:
the common column comprises a primary bit line and a complementary bit line;
the sense amplifier comprises a primary output node coupled to the primary bit line and a complementary output node coupled to the complementary bit line; and
the bit comprising the result of the logic operation is received from the primary output node of the sense amplifier.
17 . The apparatus of claim 12 , wherein:
the common column comprises a primary bit line and a complementary bit line;
the sense amplifier comprises a primary output node coupled to the primary bit line and a complementary output node coupled to the complementary bit line; and
the bit comprising the result of the logic operation is received from the complementary output node of the sense amplifier.
18 . The apparatus of claim 17 , wherein:
a fourth data memory cell and a third control memory cell are in the common column;
a fourth data word line and a third control word line are coupled to the fourth data memory cell and the third control memory cell, respectively; and
to perform the logic operation, the processor is to copy a bit from the third data memory cell to the fourth data memory cell, and concurrently activate the first, second, third and fourth data word lines, and the first, second and third control word lines.