Semiconductor switch device, manufacturing method thereof, and solid-state phase shifter
A semiconductor switch device includes a first semiconductor layer, intrinsic layers, and second semiconductor layers that are stacked. There are at least two intrinsic layers. The second semiconductor layers are in a one-to-one correspondence with the intrinsic layers, and each second semiconductor layer is stacked on a side of a corresponding intrinsic layer away from the first semiconductor layer. The first semiconductor layer forms one PIN diode together with each first intrinsic layer and each second semiconductor layer. Any two adjacent PIN diodes are electrically isolated. Automatic parameter matching between the two PIN diodes is implemented by using a geometrically symmetric figure with centers of the two PIN diodes aligned. In addition, the entire semiconductor switch device has a compact structure.
1 . A semiconductor switch device, comprising:
intrinsic layers, wherein each intrinsic layer of the intrinsic layers has a same thickness and a same doping density coefficient as each other intrinsic layer of the intrinsic layers;
a first semiconductor layer;
a backside metal layer disposed on a bottom side of the first semiconductor layer opposite to the intrinsic layers, wherein the backside metal layer comprises a titanium nickel aurum material, a titanium platinum aurum material, or a titanium aurum material;
second semiconductor layers stacked in a sandwich structure and in a one-to-one correspondence with the intrinsic layers, wherein each second semiconductor layer of the second semiconductor layers is stacked on a side of a corresponding intrinsic layer of the intrinsic layers that is away from the first semiconductor layer, wherein the first semiconductor layer, the intrinsic layers, and the second semiconductor layers form a plurality of P-type, intrinsic, N-type (PIN) diodes, and wherein each PIN diode of the plurality of PIN diodes comprises a respective portion of the first semiconductor layer, a respective intrinsic layer of the intrinsic layers, and a respective second semiconductor layer of the second semiconductor layers;
a plurality of pads disposed on top of the second semiconductor layers away from the intrinsic layers and configured to serve as external electrodes of the semiconductor switch device; and
a first insulation layer embedded in the first semiconductor layer and configured to electrically isolate adjacent intrinsic layers from each other and adjacent second semiconductor layers from each other such that adjacent PIN diodes of the plurality of PIN diodes are electrically isolated from each other,
wherein the first semiconductor layer is an N+ semiconductor layer and the second semiconductor layers are P+ semiconductor layers.
2 . The semiconductor switch device of claim 1 , wherein shapes of the second semiconductor layers and the intrinsic layers are centrosymmetric shapes.
3 . The semiconductor switch device of claim 1 ,
wherein the plurality of PIN diodes comprises at least one first PIN diode and at least one second PIN diode,
wherein an area ratio of a first surface of each first PIN diode of the at least one first PIN diode to a second surface of each second PIN diode of the at least one second PIN diode is 1:N,
wherein N is a rational number greater than or equal to 1,
wherein the first surface of each first PIN diode is of the respective second semiconductor layer of the first PIN diode, is away from the first semiconductor layer, and corresponds to a first effective area of first doped particles in the first surface, and
wherein the second surface of each second PIN diode is of the respective second semiconductor layer of the second PIN diode, is away from the first semiconductor layer, and corresponds to a second effective area of second doped particles in the second surface.
4 . The semiconductor switch device of claim 1 , wherein each PIN diode of the plurality of PIN diodes comprises respective sidewalls formed by first surfaces of the respective intrinsic layer of the PIN diode and second surfaces of the respective second semiconductor layer of the PIN diode, and wherein the semiconductor switch device further comprises a second insulation layer that is coupled to the first insulation layer and that covers the respective sidewalls of the plurality of PIN diodes.
5 . The semiconductor switch device of claim 1 , wherein the intrinsic layers are portions of a first wafer, and wherein the second semiconductors are portions of a second wafer.
6 . The semiconductor switch device of claim 1 , wherein the first insulation layer comprises a silicon dioxide material.
7 . The semiconductor switch device of claim 1 , wherein the first insulation layer comprises a silicon nitride material.
8 . The semiconductor switch device of claim 1 , wherein the pads comprise a material formed by evaporation, magnetron sputtering, or electroplating.
9 . The semiconductor switch device of claim 8 , wherein the pads comprise a titanium nickel aurum material.
10 . The semiconductor switch device of claim 8 , wherein the pads comprise a titanium platinum aurum material.
11 . The semiconductor switch device of claim 8 , wherein the pads comprise a titanium aurum material.
12 . The semiconductor switch device of claim 8 , wherein the pads comprise an aluminum material.
13 . A solid-state phase shifter, comprising:
a plurality of semiconductor switch devices, wherein each semiconductor switch device of the plurality of semiconductor switch devices comprises:
intrinsic layers, wherein each intrinsic layer of the intrinsic layers has a same thickness and a same doping density coefficient as each other intrinsic layer of the intrinsic layers;
a first semiconductor layer;
a backside metal layer disposed on a bottom side of the first semiconductor layer opposite to the intrinsic layers, wherein the backside metal layer comprises a titanium nickel aurum material, a titanium platinum aurum material, or a titanium aurum material;
second semiconductor layers stacked in a sandwich structure and in a one-to-one correspondence with the intrinsic layers, wherein each second semiconductor layer of the second semiconductor layers is stacked on a side of a corresponding intrinsic layer of the intrinsic layers that is away from the first semiconductor layer, wherein the first semiconductor layer, the intrinsic layers, and the second semiconductor layers form a plurality of P-type, intrinsic, N-type (PIN) diodes, and wherein each PIN diode of the plurality of PIN diodes comprises a respective portion of the first semiconductor layer, a respective intrinsic layer of the intrinsic layers, and a respective second semiconductor layer of the second semiconductor layers;
a plurality of pads disposed on top of the second semiconductor layers away from the intrinsic layers and configured to serve as external electrodes of the semiconductor switch device; and
a first insulation layer embedded in the first semiconductor layer and configured to electrically isolate adjacent intrinsic layers from each other and adjacent second semiconductor layers from each other such that adjacent PIN diodes of the plurality of PIN diodes are electrically isolated from each other,
wherein the first semiconductor layer is a P+ semiconductor layer and the second semiconductor layers are N+ semiconductor layers.
14 . The solid-state phase shifter of claim 13 , wherein shapes of the second semiconductor layers and the intrinsic layers are centrosymmetric shapes.
15 . The solid-state phase shifter of claim 7 , wherein there are at least two PIN diodes, wherein the at least two PIN diodes comprise at least one first PIN diode and at least one second PIN diode, wherein an area ratio of a first surface of each first PIN diode of the at least one first PIN diode to a second surface of each second PIN diode of the at least one second PIN diode is 1:N, wherein N is a rational number greater than or equal to 1, wherein the first surface of each first PIN diode of the at least one first PIN diode is of the respective second semiconductor layer of the first PIN diode, is away from the first semiconductor layer, and corresponds to a first effective area of first doped particles in the first surface, and wherein the second surface of each second PIN diode of the at least one second PIN diode is of the respective second semiconductor layer of the second PIN diode, is away from the first semiconductor layer, and corresponds to a second effective area of second doped particles in the second surface.
16 . The solid-state phase shifter of claim 13 , wherein each PIN diode of the plurality of PIN diodes comprises respective sidewalls formed by first surfaces of the respective intrinsic layer of the PIN diode and second surfaces of the respective second semiconductor layer of the PIN diode, and wherein the semiconductor switch device further comprises a second insulation layer that is coupled to the first insulation layer and that covers the respective sidewalls of the plurality of PIN diodes.
17 . The solid-state phase shifter of claim 13 , wherein the first insulation layer comprises a silicon dioxide material.
18 . The solid-state phase shifter of claim 13 , wherein the first insulation layer comprises a silicon nitride material.
19 . The solid-state phase shifter of claim 13 , wherein the semiconductor switch device further comprises a plurality of pads disposed on the second semiconductor layers.
20 . The solid-state phase shifter of claim 19 , wherein the pads comprise a titanium nickel aurum material, a titanium platinum aurum material, a titanium aurum material, or an aluminum material.