Granted Patent B2

US 12,739,045 · App. 18/713,172 · Granted Sep 15, 2026

Inventors: Dasari Durga Satya Srinivas (Bengaluru, IN); Sachin Vaish (Bengaluru, IN)

Assignee: COREEL TECHNOLOGIES INDIA PRIVATE LIMITED

H04J3/0667H04J3/0641

Abstract

Claims (73)

1 . A method of creating multi-port network synchronization bridge between a plurality of ethernet ports and a processor via a programmable Gate Array (PGA), the method comprising:

segregating, by the PGA, a PTP message associated with each ethernet port among the plurality of ethernet ports into one of:

a critical message comprising at least one of a Sync message and a Sync Follow-up message, and

a non-critical message comprising at least one of an Announce message, a delay Request message and a delay Response message;

determining, by the processor and the PGA, based on the PTP message one ethernet port as a Slave port and one or more ethernet ports as one or more Master ports;

processing, by the PGA, the critical message by:

determining, based on segregation of the critical message, whether a difference between a master clock and a system clock, exceeds a predefined threshold; and

compensating, the difference between the master clock and the system clock based on the determination within a predefined range; and

processing, by the processor, the non-critical message based on a plurality of Transmit (Tx) pulses and a plurality of Receive (Rx) pulses generated by the PGA.

2 . The method as claimed in claim 1 , wherein prior to the processing the non-critical message, the method comprising:

transmitting the non-critical message from the PGA to the processor through one or more data bus.

3 . The method as claimed in claim 1 , wherein processing, by the processor, the non-critical message comprises processing the non-critical message without using a driver or libraries or a package.

4 . The method as claimed in claim 1 , wherein the method further comprising:

determining if the announce message is received at least at one of the plurality of ethernet ports;

determining if there is variation in one or more clock parameters associated with the at least one of the plurality of ethernet ports;

copying the announce message to a Receive (Rx) buffer of the PGA on determining that there is variation in the one or more clock parameters; and

determining, by the processor, a best master clock (BMC) based on the announce message stored in the Rx buffer.

5 . The method as claimed in claim 1 , further comprising:

determining, by the PGA, if the Sync message or Sync Follow-up message is received at least at one of the plurality of ethernet ports; and

copying, by the PGA, the received Sync message or Sync Follow-up message to a transmit (Tx) buffer of the PGA based on the determination.

6 . The method as claimed in claim 1 , further comprising:

determining, by the PGA, if a transmit (Tx) pulse signal is generated periodically and received by the processor;

generating, by the processor, the non-critical periodic PTP transmit messages based on the determination, and

transmitting, by the PGA, the PTP message from a transmit (Tx) buffer based on the generation, after retrieving the PTP messages.

7 . The method as claimed in claim 1 , further comprising:

determining, by the PGA, if a receive (Rx) pulse signal is generated periodically and received by the processor;

retrieving, by the processor, the non-critical messages for the processing, based on the determination.

8 . The method as claimed in claim 1 , wherein the determining, by the processor and the PGA, based on the PTP message one ethernet port as the Slave port and one or more ethernet ports as one or more Master ports is based on superiority or inferiority of the clock parameters of each port if the announce message is received at least at one of the plurality of ethernet ports;

wherein the one or more clock parameters are extracted from the Announce message via the processor.

9 . The method as claimed in claim 1 , further comprising:

determining whether the non-critical message received by the processor from the PGA via the data bus is a Pdelay request message;

generating, by the processor, a Pdelay response, if the Pdelay request message is received;

transmitting, by the processor, the Pdelay response to the transmit (Tx) buffer; and

calculating, by the processor, a network path delay, if the Pdelay response is received in the receive (Rx) buffer.

10 . The method as claimed in claim 1 , further comprising: generating, by the processor, a plurality of periodic messages corresponding to all of the plurality of ethernet ports, if periodic transmit (Tx) pulses or interrupt pulse is received.

11 . The method as claimed in claim 1 , further comprising: updating, by the PGA, a correction field of the Sync Follow-up message of the critical message based on timestamping and a processing delay computed by the PGA.

12 . A system for creating multi-port network synchronization bridge between a plurality of ethernet ports and a processor via a programmable Gate Array (PGA), the system comprising:

the PGA configured to:

segregate a PTP message associated with each ethernet port among the plurality of ethernet ports into one of:

a critical message comprising at least one of a Sync message and a Sync Follow-up message, and

a non-critical message comprising at least one of an Announce message,

a delay Request message and a delay Response message;

process the critical message by:

determining, based on segregation of the critical message, whether a difference between a Master clock and a system clock, exceeds a predefined threshold; and

compensating, the difference between the Master clock and the system clock based on the determination within a predefined range of precision; and

the processor is configured to:

process the non-critical message based on a plurality of Transmit (Tx) pulses and a plurality of Receive (Rx) pulses generated by the PGA;

wherein the processor and the PGA, are adapted to determine, based on the PTP message one ethernet port to be assigned as a Slave port and one or more ethernet ports to be assigned as one or more Master ports.

13 . The system as claimed in claim 12 , wherein prior to the processing of the non-critical message, the system is configured for transmitting the non-critical message from the PGA to the processor through one or more data bus.

14 . The system as claimed in claim 12 , wherein the processor is configured to process the non-critical message without using a driver or a libraries or a package.

15 . The system as claimed in claim 12 , wherein the processor is configured to:

determine if the announce message is received at least at one of the plurality of ethernet ports;

determine if there is variation in one or more clock parameters associated with the at least one of the plurality of ethernet ports;

copy the announce message to a Receive (Rx) buffer of the PGA on determining that there is variation in the one or more clock parameters; and

determine a best master clock (BMC) based on the announce message stored in the Rx buffer.

16 . The system as claimed in claim 12 , the PGA is configured to:

determine if the Sync message or Sync Follow-up message is received at least at one of the plurality of ethernet ports; and

copy the received Sync message or Sync Follow-up message to a Transmit (Tx) buffer of the PGA based on the determination.

17 . The system as claimed in claim 12 , wherein the system is configured to:

determine, by the PGA, if a transmit (Tx) pulse signal is generated periodically and received by the processor;

generate, by the processor, the non-critical periodic PTP transmit messages based on the determination, and

transmit, by the PGA, the PTP message from a transmit (Tx) buffer based on the generation, after retrieving the PTP messages.

18 . The system as claimed in claim 12 , wherein the system is configured to:

determine, by the PGA, if a receive (Rx) pulse signal is generated periodically and received by the processor;

retrieve, by the processor, the non-critical messages for the processing, based on the determination.

19 . The system as claimed in claim 12 , wherein the system is configured to:

determine, by the processor and the PGA, based on the PTP message one ethernet port as the Slave port and one or more ethernet ports as one or more Master ports is based on superiority or inferiority of the clock parameters of each port if the announce message is received at least at one of the plurality of ethernet ports

wherein the one or more clock parameters are extracted from the Announce message via the processor.

20 . The system as claimed in claim 12 , wherein the system is configured to:

determine whether the non-critical message received by the processor from the PGA via the data bus is a Pdelay request message;

generate, by the processor, a Pdelay response, if the Pdelay request message is received;

transmit, by the processor, the Pdelay response to the transmit (Tx) buffer; and

calculate, by the processor, a network path delay, if the Pdelay response is received in the receive (Rx) buffer.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (28)