Method of fine pitch pattering for semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device includes forming a plurality of reference patterns and a peripheral pattern on a feature layer by using a first material such that the peripheral pattern is connected to end portions of the plurality of reference patterns; forming a plurality of first spacers on both sidewalls of each of the plurality of reference patterns by using a second material; removing the plurality of reference patterns; forming a plurality of second spacers on both sidewalls of each of the plurality of first spacers by using the first material; removing the plurality of first spacers so that the plurality of second spacers and the peripheral pattern remain on the feature layer; and patterning the feature layer by using the plurality of second spacers and the peripheral pattern as an etch mask.
1 . A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of reference patterns and a peripheral pattern on a feature layer using a first material such that the peripheral pattern is connected to end portions of the plurality of reference patterns;
forming a plurality of first spacers on opposite sidewalls of each of the plurality of reference patterns using a second material;
removing the plurality of reference patterns;
forming a plurality of second spacers on opposite sidewalls of each of the plurality of first spacers using the first material, wherein the feature layer is exposed between neighboring pairs of first spacers of the plurality of first spacers;
forming a gap-fill insulation layer to cover the feature layer, the plurality of first spacers, and the plurality of second spacers, the gap-fill insulation layer contacting the feature layer;
removing the plurality of first spacers and the gap-fill insulation layer so that the plurality of second spacers and the peripheral pattern remain on the feature layer with the feature layer exposed between neighboring pairs of second spacers of the plurality of second spacers; and
patterning the feature layer using the plurality of second spacers and the peripheral pattern as an etch mask.
2 . The method as claimed in claim 1 , wherein:
the first material includes polysilicon or amorphous silicon, and
the second material includes silicon oxide, silicon nitride, or silicon oxynitride.
3 . The method as claimed in claim 1 , wherein, in a plan view, the peripheral pattern surrounds the plurality of reference patterns.
4 . The method as claimed in claim 1 , wherein:
F is a target feature size,
the plurality of reference patterns are arranged at a pitch of 8 F,
the plurality of first spacers are arranged at a pitch of 4 F, and
the plurality of second spacers are arranged at a pitch of 2 F.
5 . The method as claimed in claim 1 , wherein forming the plurality of first spacers includes:
forming a first spacer layer on the feature layer to cover the plurality of reference patterns and the peripheral pattern;
forming a mask pattern on the first spacer layer such that the mask pattern does not cover a first portion of the first spacer layer on the plurality of reference patterns and does cover a second portion of the first spacer layer on the peripheral pattern; and
removing some portions of the first portion of the first spacer layer from a top surface of each of the plurality of reference patterns such that the plurality of first spacers remain on both sidewalls of the plurality of reference patterns.
6 . The method as claimed in claim 5 , wherein, in the removing of the plurality of reference patterns, the second portion of the first spacer layer remains and covers a top surface of the peripheral pattern.
7 . The method as claimed in claim 5 , further comprising performing a planarization process on an upper portion of the gap-fill insulation layer such that a difference between a top level of the gap-fill insulation layer on the second portion of the first spacer layer and a top level of the gap-fill insulation layer on the plurality of second spacers is decreased, after forming the gap-fill insulation layer.
8 . The method as claimed in claim 5 , wherein the gap-fill insulation layer includes silicon oxide, silicon nitride, silicon oxynitride, or a spin-on hardmask (SOH).
9 . A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of reference patterns and a peripheral pattern on a feature layer such that the peripheral pattern is connected to end portions of the plurality of reference patterns;
forming a plurality of first spacers on both sidewalls of each of the plurality of reference patterns;
removing the plurality of reference patterns;
forming a plurality of second spacers on opposite sidewalls of each of the plurality of first spacers;
forming a gap-fill insulation layer on the feature layer such that the gap-fill insulation layer fills a space between the plurality of second spacers and contacts the feature layer;
removing the gap-fill insulation layer and the plurality of first spacers such that the plurality of second spacers and the peripheral pattern remain on the feature layer; and
patterning the feature layer using the plurality of second spacers and the peripheral pattern as an etch mask.
10 . The method as claimed in claim 9 , wherein:
the plurality of reference patterns, the peripheral pattern, and the plurality of second spacers include polysilicon or amorphous silicon, and
the plurality of first spacers and the gap-fill insulation layer include silicon oxide, silicon nitride, or silicon oxynitride.
11 . The method as claimed in claim 9 , wherein forming the plurality of first spacers includes:
forming a first spacer layer on the feature layer to cover the plurality of reference patterns and the peripheral pattern;
forming a mask pattern on the first spacer layer such that the mask pattern does not cover a first portion of the first spacer layer on the plurality of reference patterns and does cover a second portion of the first spacer layer on the peripheral pattern; and
removing some portions of the first portion of the first spacer layer from a top surface of each of the plurality of reference patterns such that the plurality of first spacers remain on the opposite sidewalls of the plurality of reference patterns.
12 . The method as claimed in claim 11 , wherein, in the removing of the plurality of reference patterns, the second portion of the first spacer layer remains and covers a top surface of the peripheral pattern.
13 . The method as claimed in claim 11 , further comprising performing a planarization process on an upper portion of the gap-fill insulation layer such that a difference between a top level of the gap-fill insulation layer on the second portion of the first spacer layer and a top level of the gap-fill insulation layer on the plurality of second spacers is decreased, after forming the gap-fill insulation layer.
14 . The method as claimed in claim 9 , wherein, in a plan view, the peripheral pattern surrounds the plurality of reference patterns.
15 . The method as claimed in claim 9 , wherein:
F is a target feature size,
the plurality of reference patterns are arranged at a pitch of 8 F,
the plurality of first spacers are arranged at a pitch of 4 F, and
the plurality of second spacers are arranged at a pitch of 2 F.
16 . A method of manufacturing a semiconductor device, the method comprising:
providing a substrate including a cell array region and a boundary region;
forming a feature layer on the substrate;
forming a plurality of reference patterns and a peripheral pattern on the feature layer using a first material, the plurality of reference patterns being on the cell array region, and the peripheral pattern being connected to end portions of the plurality of reference patterns and on the boundary region;
forming a plurality of first spacers on opposite sidewalls of each of the plurality of reference patterns using a second material;
removing the plurality of reference patterns;
forming a plurality of second spacers on opposite sidewalls of each of the plurality of first spacers by using the first material, wherein the feature layer is exposed between neighboring pairs of first spacers of the plurality of first spacers;
forming a gap-fill insulation layer to cover the feature layer, the plurality of first spacers, and the plurality of second spacers, the gap-fill insulation layer contacting the feature layer;
removing the plurality of first spacers and the gap-fill insulation layer such that the plurality of second spacers and the peripheral pattern remain on the feature layer with the feature layer exposed between neighboring pairs of second spacers of the plurality of second spacers;
patterning the feature layer using the plurality of second spacers and the peripheral pattern as an etch mask; and
removing a portion of the substrate using the feature layer as an etch mask to form a device isolation trench.
17 . The method as claimed in claim 16 , wherein:
forming the plurality of first spacers includes:
forming a first spacer layer on the feature layer to cover the plurality of reference patterns and the peripheral pattern;
forming a mask pattern on the first spacer layer such that the mask pattern does not cover a first portion of the first spacer layer on the plurality of reference patterns and does cover a second portion of the first spacer layer on the peripheral pattern; and
removing some portions of the first portion of the first spacer layer from a top surface of each of the plurality of reference patterns such that the plurality of first spacers remain on both sidewalls of the plurality of reference patterns, and
in the removing of the plurality of reference patterns from the feature layer, the second portion of the first spacer layer remains and covers a top surface of the peripheral pattern.
18 . The method as claimed in claim 17 , further comprising performing a planarization process on an upper portion of the gap-fill insulation layer such that a difference between a top level of the gap-fill insulation layer on the second portion of the first spacer layer and a top level of the gap-fill insulation layer on the plurality of second spacers is decreased, after forming the gap-fill insulation layer.