IP Library › Granted Patent US 12,740,483
Granted Patent B2
US 12,740,483 · App. 18/308,885 · Granted Sep 15, 2026

Electronic circuit fabrication

Inventor: David Patten (Austin, TX)
Assignee: Cirrus Logic Inc.
H10W90/00H10W74/01H10W74/111H10W72/877H10W90/724H10W90/732
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Quick Facts
Patent No.
US 12,740,483
App. No.
18/308,885
Granted
Sep 15, 2026
Kind
B2
Abstract

This application describes electronic circuit packages and methods of manufacture. The package ( 100, 300 ) includes a primary integrated circuit die ( 101 ) with a smaller secondary integrated circuit die ( 102 ) attached to a first surface of the primary integrated circuit die in a first location. A first set of electrical connectors ( 103 ) extend from the first surface of the primary integrated circuit die outside the first location to a package connection layer ( 106 ) to provide electrical connection between the package connection layer and the primary integrated circuit die. An intermediate layer ( 108 ) of dielectric or insulating material extends between the primary integrated circuit die and the package connection layer so that the dielectric or insulating material surrounds the first set of electrical connectors and there is at least some dielectric or insulating material between the second integrated circuit die and the package connection layer.

Claims (8)

1 . A method of forming an electronic circuit package comprising:

taking a primary wafer having a first surface and a second surface, wherein the primary wafer comprises one or more integrated circuits in respective circuit areas and comprises, for each circuit area, a first set of electrical connectors outside of a first location that extend from the first surface of the wafer to a first plane;

for each circuit area, attaching a secondary integrated circuit die to the first surface of the primary wafer in the first location;

forming an intermediate layer of dielectric or insulating material that extends between the first surface of the primary wafer to the first plane so that, for each circuit area, the dielectric or insulating material surrounds the first set of electrical connectors and there is at least some dielectric or insulating material between the second integrated circuit die and the first plane; and

forming, for each circuit area, a package connection layer over the intermediate layer of dielectric or insulating material.

2 . The method of claim 1 wherein the dielectric or insulating material is applied as fluid or a film so as to, for each circuit area, flow around and over the secondary integrated circuit die and the first set of electrical connectors and then cured or treated to set or hardened.

3 . The method of claim 1 wherein the step of forming the intermediate layer of dielectric or insulating material comprises applying a lamination film to the first surface of the primary wafer under heat and/or pressure and subsequently curing the lamination film.

4 . The method of claim 1 further comprising dicing the primary wafer into individual die corresponding to each circuit area wherein the primary wafer comprises alignment marks to aid in dicing the primary wafer and wherein the intermediate layer of dielectric or insulating material is formed to be sufficient transparent to allow the alignment marks to be observed at visible wavelengths.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2026
From: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
To: CIRRUS LOGIC, INC.
Reel/Frame 074434/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2023
From: PATTEN, DAVID
To: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
Reel/Frame 063687/0789 →
Priority Claims (1)
GB 2213545 · Sep 15, 2022 · national
Continuity (2)
Provisional Application 63339076 · May 6, 2022
Related Publication 20240128235A1 · Apr 18, 2024
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