Synchronous microthreading
Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
1 . A method comprising:
saving state from all executing microthreads to a microthread state save area upon a detection of a fault by at least one microthread during microthread execution;
marking each fault in a bit vector indicating which microthread faulted, wherein each microthread has an independent register state;
transitioning to a host execution mode and setting a microthread execution event type indication in event information to be delivered by an event delivery logic;
using a fault handler to handle the fault using the saved state;
restarting microthreaded execution.
2 . The method of claim 1 , wherein microcode saves the state.
3 . The method of claim 1 , wherein the state includes error codes and register state.
4 . The method of claim 1 , wherein a retirement unit detects the fault.
5 . The method of claim 1 , wherein the event information includes an error code, an event vector, and the event type.
6 . The method of claim 5 , wherein the event vector indicates one or more of faults of divide, debug, overflow, invalid opcode, general protection, page fault, alignment check, machine check, and vector exception.
7 . The method of claim 1 , further comprising:
halting all microthreads upon a detection of a fault.
8 . An apparatus comprising:
a processor core including microcode to:
save state from all executing microthreads to a microthread state save area upon a detection of a fault by at least one microthread during microthread execution, wherein each microthread has an independent register state,
mark each fault in a bit vector indicating which microthread faulted, and
transition to a host execution mode and setting a microthread execution event type indication in event information to be delivered by an event delivery logic;
a fault handler to handle the fault using the saved state, wherein the microcode is to restart microthreaded execution upon the fault being handled.
9 . The apparatus of claim 8 , wherein the state is to include error codes and register state.
10 . The apparatus of claim 8 , wherein a retirement unit is to detect the fault.
11 . The apparatus of claim 8 , wherein the event information is to include an error code, an event vector, and the event type.
12 . The apparatus of claim 11 , wherein the event vector is to indicate one or more of faults of divide, debug, overflow, invalid opcode, general protection, page fault, alignment check, machine check, and vector exception.
13 . The apparatus of claim 8 , wherein the microcode is further to halt all microthreads upon a detection of a fault.
14 . A system comprising:
memory to store microthread save state;
a hardware processor core including microcode to:
save state from all executing microthreads to the microthread state save upon a detection of a fault by at least one microthread during microthread execution, wherein each microthread has an independent register state,
mark each fault in a bit vector indicating which microthread faulted, and
transition to a host execution mode and setting a microthread execution event type indication in event information to be delivered by an event delivery logic; and
a fault handler to handle the fault using the saved state, wherein the microcode is to restart microthreaded execution upon the fault being handled.
15 . The system of claim 14 , wherein the state is to include error codes and register state.
16 . The system of claim 14 , wherein a retirement unit is to detect the fault.
17 . The system of claim 14 , wherein the event information is to include an error code, an event vector, and the event type.
18 . The system of claim 17 , wherein the event vector is to indicate one or more of faults of divide, debug, overflow, invalid opcode, general protection, page fault, alignment check, machine check, and vector exception.
19 . The system of claim 15 , wherein the microcode is further to halt all microthreads upon a detection of a fault.