Generative self-supervised learning to transform circuit netlists
Self-supervised machine learning is applied to combinational gate sizing based on an input circuit netlist. A transformer neural network architecture is disclosed to select gate sizes along paths of the network between primary inputs/outputs and/or sequential logic elements. The gate size selections may be optimized along dimensions such as path delay, path power consumption, and path circuit area.
1 . A transformer network for setting characteristics of gates in a circuit, the transformer network trained with gate characteristic distributions from a technology library, the transformer network comprising:
an encoder configured to transform a sequence of gate types for a combinatorial circuit path in the circuit into encoder outputs; and
a decoder configured to transform the encoder outputs, an effort level setting, and the sequence of gate types into a sequence of gate sizes for the combinatorial circuit path,
wherein the effort level setting comprises a ratio of a median signal propagation delay and an actual signal propagation delay for the sequence of gate types.
2 . The transformer network of claim 1 , wherein the median delay is a sum of a median fanout-of-four (FO4) delay of each gate type in the the sequence of gate types.
3 . The transformer network of claim 1 , further comprising:
a weighted cross-entropy loss function employing as a weight value a normalized mean square error (MSE) of FO4 delay values of the gates in the sequence of gate types.
4 . The transformer network of claim 1 , the transformer network further configured to:
select sizes of gates in the sequence of gate types to optimize timing, power, area, or combinations thereof for the sequence of gate types.
5 . The transformer network of claim 1 , wherein the transformer network models the propagation of signals through the sequence of gate types.
6 . The transformer network of claim 1 , wherein the encoder and the decoder each comprise exactly two encoding and decoding stages, respectively.
7 . A method for setting gate sizes in a circuit path, the method comprising:
applying, to an encoder of a transformer network, gate types for each gate in the circuit path;
applying, to a decoder of the transformer network, outputs of the encoder, and a token sequence comprising as a starting token an effort level and a first gate type of the gate type sequence, whereafter the token sequence comprises <predicted k th gate size, (k+1) th gate type> pairs and k is a gate position index in the circuit path; and
the transformer network generating a sequence of the gate sizes from the gate types, effort level, and predicted gate sizes.
8 . The method of claim 7 , wherein the circuit path comprises a combinatorial gate sequence between a start point and an endpoint, and wherein the start point comprises one of a primary input and a first synchronous circuit element, and wherein the endpoint comprises one of a primary output and a second synchronous circuit element.
9 . The method of claim 7 , wherein the effort level setting comprises a ratio of a median delay and an actual delay for the circuit path.
10 . The method of claim 9 , wherein the median delay is a sum of a median fanout-of-four (FO4) delay of each gate type in the circuit path.
11 . The method network of claim 7 , further comprising:
utilizing in the transformer network a loss function weighted by a mean square error (MSE) of FO4 delay values for the gates in the circuit path.
12 . The method of claim 7 , further comprising:
setting the gate sizes to optimize timing, power, area, or combinations thereof for the circuit path.
13 . The method of claim 7 , wherein the encoder comprises a plurality of encoding stages and each encoding stage outputs to a corresponding stage of the decoder.
14 . A system comprising:
at least one processor; and
at least one memory implementing logic to:
operate a transformer network encoder to transform a sequence of gate types for a combinatorial circuit path into encoder outputs;
apply the encoder outputs to a decoder of the transformer network;
further apply to the decoder a token sequence comprising an effort level, the sequence of gate types, and predicted sizes for gates of the combinatorial circuit path; and
operate the decoder to generate a sequence of gate sizes for the combinatorial circuit path from the gate types, effort level, encoder outputs, and predicted gate sizes.
15 . The system of claim 14 , wherein the at least one processor comprises a graphics processing unit.
16 . The system of claim 14 , wherein the combinatorial circuit path comprises a start point and an endpoint, and wherein the start point comprises one of a primary input and a first synchronous circuit element, and wherein the endpoint comprises one of a primary output and a second synchronous circuit element.
17 . The system of claim 14 , wherein the effort level setting comprises a ratio of a median delay and an actual delay for the circuit path.
18 . The system of claim 17 , wherein the median delay is a sum of a median fanout-of-four (FO4) delay of each gate type in the circuit path.
19 . The system of claim 14 , the memory further implementing logic to:
implement a loss function weighted by a mean square error (MSE) of FO4 delay values for the gates of the combinatorial circuit path.
20 . A process comprising:
operating a transformer network encoder to transform a sequence of gate types for a combinatorial circuit path into encoder outputs;
applying the encoder outputs to a decoder of the transformer network;
further applying to the decoder a token sequence comprising an effort level, the sequence of gate types, and predicted sizes for gates of the combinatorial circuit path; and
operating the decoder to generate a sequence of gate sizes for the combinatorial circuit path from the gate types, effort level, encoder outputs, and predicted gate sizes.